mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 04:22:57 +02:00
17c114f241
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
95 lines
2.0 KiB
Plaintext
95 lines
2.0 KiB
Plaintext
# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m4 | FileCheck %s
|
|
|
|
#------------------------------------------------------------------------------
|
|
# MRS
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: mrs r0, apsr
|
|
# CHECK: mrs r0, iapsr
|
|
# CHECK: mrs r0, eapsr
|
|
# CHECK: mrs r0, xpsr
|
|
# CHECK: mrs r0, ipsr
|
|
# CHECK: mrs r0, epsr
|
|
# CHECK: mrs r0, iepsr
|
|
# CHECK: mrs r0, msp
|
|
# CHECK: mrs r0, psp
|
|
# CHECK: mrs r0, primask
|
|
# CHECK: mrs r0, basepri
|
|
# CHECK: mrs r0, basepri_max
|
|
# CHECK: mrs r0, faultmask
|
|
# CHECK: mrs r0, control
|
|
|
|
0xef 0xf3 0x00 0x80
|
|
0xef 0xf3 0x01 0x80
|
|
0xef 0xf3 0x02 0x80
|
|
0xef 0xf3 0x03 0x80
|
|
0xef 0xf3 0x05 0x80
|
|
0xef 0xf3 0x06 0x80
|
|
0xef 0xf3 0x07 0x80
|
|
0xef 0xf3 0x08 0x80
|
|
0xef 0xf3 0x09 0x80
|
|
0xef 0xf3 0x10 0x80
|
|
0xef 0xf3 0x11 0x80
|
|
0xef 0xf3 0x12 0x80
|
|
0xef 0xf3 0x13 0x80
|
|
0xef 0xf3 0x14 0x80
|
|
|
|
|
|
#------------------------------------------------------------------------------
|
|
# MSR
|
|
#------------------------------------------------------------------------------
|
|
|
|
# CHECK: msr apsr, r0
|
|
# CHECK: msr apsr_g, r0
|
|
# CHECK: msr apsr_nzcvqg, r0
|
|
|
|
0x80 0xf3 0x00 0x88
|
|
0x80 0xf3 0x00 0x84
|
|
0x80 0xf3 0x00 0x8c
|
|
|
|
# CHECK: msr iapsr, r0
|
|
# CHECK: msr iapsr_g, r0
|
|
# CHECK: msr iapsr_nzcvqg, r0
|
|
|
|
0x80 0xf3 0x01 0x88
|
|
0x80 0xf3 0x01 0x84
|
|
0x80 0xf3 0x01 0x8c
|
|
|
|
# CHECK: msr eapsr, r0
|
|
# CHECK: msr eapsr_g, r0
|
|
# CHECK: msr eapsr_nzcvqg, r0
|
|
|
|
0x80 0xf3 0x02 0x88
|
|
0x80 0xf3 0x02 0x84
|
|
0x80 0xf3 0x02 0x8c
|
|
|
|
# CHECK: msr xpsr, r0
|
|
# CHECK: msr xpsr_g, r0
|
|
# CHECK: msr xpsr_nzcvqg, r0
|
|
|
|
0x80 0xf3 0x03 0x88
|
|
0x80 0xf3 0x03 0x84
|
|
0x80 0xf3 0x03 0x8c
|
|
|
|
# CHECK: msr ipsr, r0
|
|
# CHECK: msr epsr, r0
|
|
# CHECK: msr iepsr, r0
|
|
# CHECK: msr msp, r0
|
|
# CHECK: msr psp, r0
|
|
# CHECK: msr primask, r0
|
|
# CHECK: msr basepri, r0
|
|
# CHECK: msr basepri_max, r0
|
|
# CHECK: msr faultmask, r0
|
|
# CHECK: msr control, r0
|
|
|
|
0x80 0xf3 0x05 0x88
|
|
0x80 0xf3 0x06 0x88
|
|
0x80 0xf3 0x07 0x88
|
|
0x80 0xf3 0x08 0x88
|
|
0x80 0xf3 0x09 0x88
|
|
0x80 0xf3 0x10 0x88
|
|
0x80 0xf3 0x11 0x88
|
|
0x80 0xf3 0x12 0x88
|
|
0x80 0xf3 0x13 0x88
|
|
0x80 0xf3 0x14 0x88
|