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9091dc1c0e
We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
44 lines
1.4 KiB
LLVM
44 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=thumbv7-apple-ios7.0 -o - %s -verify-machineinstrs | FileCheck %s
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; The base register for the store is killed by the last instruction, but is
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; actually also used during as part of the store itself. If an extra ADD is
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; inserted, it should not kill the base.
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define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) {
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; CHECK-LABEL: test_base_kill:
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; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4
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; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
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%addr.1 = getelementptr i32, i32* %addr, i32 1
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store i32 %v0, i32* %addr.1
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%addr.2 = getelementptr i32, i32* %addr, i32 2
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store i32 %v1, i32* %addr.2
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%addr.3 = getelementptr i32, i32* %addr, i32 3
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%val = ptrtoint i32* %addr to i32
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store i32 %val, i32* %addr.3
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ret void
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}
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; Similar, but it's not sufficient to look at just the last instruction (where
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; liveness of the base is determined). An intervening instruction might be moved
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; past it to form the STM.
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define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) {
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; CHECK-LABEL: test_base_kill_mid:
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; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4
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; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
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%addr.1 = getelementptr i32, i32* %addr, i32 1
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store i32 %v0, i32* %addr.1
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%addr.2 = getelementptr i32, i32* %addr, i32 2
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%val = ptrtoint i32* %addr to i32
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store i32 %val, i32* %addr.2
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%addr.3 = getelementptr i32, i32* %addr, i32 3
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store i32 %v1, i32* %addr.3
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ret void
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}
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