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1a0155bc19
The isReMaterlizable flag is somewhat confusing, unlike most other instruction flags it is currently interpreted as a hint (mightBeRematerializable would be a better name). While LUI is always rematerialisable, for an instruction like ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on the logic in the latter to pick out instances of ADDI that really are rematerializable. The isReMaterializable flag does make a difference on a variety of test programs. The recently committed remat.ll test case demonstrates how stack usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the Proc0 function in dhrystone reduces from 192 bytes to 112 bytes. For the sake of completeness, this patch also implements RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of places, it doesn't seem to result in different codegen for any programs I've thrown at it. However, it is called in the rematerialisation codepath and it seems sensible to implement something correct here. Differential Revision: https://reviews.llvm.org/D46182 llvm-svn: 332617
60 lines
1.8 KiB
C++
60 lines
1.8 KiB
C++
//===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "RISCVGenRegisterInfo.inc"
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namespace llvm {
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struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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RISCVRegisterInfo(unsigned HwMode);
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool isConstantPhysReg(unsigned PhysReg) const override;
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const uint32_t *getNoPreservedMask() const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
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return true;
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}
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};
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}
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#endif
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