Alex Bradbury 1a0155bc19 [RISCV] Set isReMaterializable on ADDI and LUI instructions ... The isReMaterlizable flag is somewhat confusing, unlike most other instruction flags it is currently interpreted as a hint (mightBeRematerializable would be a better name). While LUI is always rematerialisable, for an instruction like ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on the logic in the latter to pick out instances of ADDI that really are rematerializable. The isReMaterializable flag does make a difference on a variety of test programs. The recently committed remat.ll test case demonstrates how stack usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the Proc0 function in dhrystone reduces from 192 bytes to 112 bytes. For the sake of completeness, this patch also implements RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of places, it doesn't seem to result in different codegen for any programs I've thrown at it. However, it is called in the rematerialisation codepath and it seems sensible to implement something correct here. Differential Revision: https://reviews.llvm.org/D46182 llvm-svn: 332617		2018-05-17 15:51:37 +00:00
..
AsmParser	[RISCV] Add support for .half, .hword, .word, .dword directives	2018-05-17 05:58:08 +00:00
Disassembler	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
InstPrinter	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
MCTargetDesc	[RISCV] Add support for .half, .hword, .word, .dword directives	2018-05-17 05:58:08 +00:00
TargetInfo	Fix RISCV build after r318352	2017-11-16 18:39:31 +00:00
CMakeLists.txt	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
LLVMBuild.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.h	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCV.td	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVCallingConv.td	[RISCV] Add custom CC_RISCV calling convention and improved call support	2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVFrameLowering.h	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVInstrFormats.td	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVInstrFormatsC.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.h	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVInstrInfoA.td	[RISCV] MC layer support for the standard RV64A instruction set extension	2017-12-07 10:59:12 +00:00
RISCVInstrInfoC.td	[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0	2018-04-12 19:22:40 +00:00
RISCVInstrInfoD.td	[RISCV] Codegen support for RV32D floating point comparison operations	2018-04-12 05:50:06 +00:00
RISCVInstrInfoF.td	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfoM.td	[RISCV] Codegen support for the standard RV32M instruction set extension	2018-01-18 12:36:38 +00:00
RISCVISelDAGToDAG.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
RISCVISelLowering.cpp	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
RISCVISelLowering.h	[RISCV] Implement isZextFree	2018-04-26 14:04:18 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv	2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVRegisterInfo.cpp	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00