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1fde07b2dc
This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
118 lines
2.0 KiB
Plaintext
118 lines
2.0 KiB
Plaintext
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
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# CHECK: popc %g1, %g2
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0x85 0x70 0x00 0x01
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# CHECK: ta %icc, %i5
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0x91 0xd0 0x00 0x1d
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# CHECK: ta %icc, 82
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0x91 0xd0 0x20 0x52
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# CHECK: ta %icc, %g1 + %i2
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0x91 0xd0 0x40 0x1a
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# CHECK: ta %icc, %i5 + 41
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0x91 0xd7 0x60 0x29
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# CHECK: tn %icc, %i5
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0x81 0xd0 0x00 0x1d
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# CHECK: tne %icc, 82
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0x93 0xd0 0x20 0x52
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# CHECK: te %icc, %g1 + %i2
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0x83 0xd0 0x40 0x1a
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# CHECK: tg %icc, %i5 + 41
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0x95 0xd7 0x60 0x29
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# CHECK: tle %icc, %i5
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0x85 0xd0 0x00 0x1d
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# CHECK: tge %icc, 82
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0x97 0xd0 0x20 0x52
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# CHECK: tl %icc, %g1 + %i2
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0x87 0xd0 0x40 0x1a
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# CHECK: tgu %icc, %i5 + 41
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0x99 0xd7 0x60 0x29
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# CHECK: tleu %icc, %i5
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0x89 0xd0 0x00 0x1d
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# CHECK: tcc %icc, 82
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0x9b 0xd0 0x20 0x52
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# CHECK: tcs %icc, %g1 + %i2
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0x8b 0xd0 0x40 0x1a
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# CHECK: tpos %icc, %i5 + 41
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0x9d 0xd7 0x60 0x29
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# CHECK: tneg %icc, %i5
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0x8d 0xd0 0x00 0x1d
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# CHECK: tvc %icc, 82
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0x9f 0xd0 0x20 0x52
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# CHECK: tvs %icc, %g1 + %i2
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0x8f 0xd0 0x40 0x1a
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# CHECK: ta %xcc, %i5
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0x91 0xd0 0x10 0x1d
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# CHECK: ta %xcc, 82
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0x91 0xd0 0x30 0x52
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# CHECK: ta %xcc, %g1 + %i2
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0x91 0xd0 0x50 0x1a
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# CHECK: ta %xcc, %i5 + 41
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0x91 0xd7 0x70 0x29
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# CHECK: tn %xcc, %i5
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0x81 0xd0 0x10 0x1d
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# CHECK: tne %xcc, 82
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0x93 0xd0 0x30 0x52
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# CHECK: te %xcc, %g1 + %i2
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0x83 0xd0 0x50 0x1a
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# CHECK: tg %xcc, %i5 + 41
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0x95 0xd7 0x70 0x29
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# CHECK: tle %xcc, %i5
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0x85 0xd0 0x10 0x1d
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# CHECK: tge %xcc, 82
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0x97 0xd0 0x30 0x52
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# CHECK: tl %xcc, %g1 + %i2
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0x87 0xd0 0x50 0x1a
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# CHECK: tgu %xcc, %i5 + 41
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0x99 0xd7 0x70 0x29
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# CHECK: tleu %xcc, %i5
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0x89 0xd0 0x10 0x1d
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# CHECK: tcc %xcc, 82
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0x9b 0xd0 0x30 0x52
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# CHECK: tcs %xcc, %g1 + %i2
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0x8b 0xd0 0x50 0x1a
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# CHECK: tpos %xcc, %i5 + 41
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0x9d 0xd7 0x70 0x29
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# CHECK: tneg %xcc, %i5
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0x8d 0xd0 0x10 0x1d
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# CHECK: tvc %xcc, 82
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0x9f 0xd0 0x30 0x52
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# CHECK: tvs %xcc, %g1 + %i2
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0x8f 0xd0 0x50 0x1a |