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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
27 lines
749 B
LLVM
27 lines
749 B
LLVM
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
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@i = global i32 1, align 4
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@j = global i32 2, align 4
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@a = global i32 5, align 4
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@.str = private unnamed_addr constant [8 x i8] c"%i = 1\0A\00", align 1
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@k = common global i32 0, align 4
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define void @t() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
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entry:
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%0 = load i32, i32* @a, align 4
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%cmp = icmp ne i32 %0, 10
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%1 = load i32, i32* @i, align 4
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%2 = load i32, i32* @j, align 4
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%cond = select i1 %cmp, i32 %1, i32 %2
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store i32 %cond, i32* @i, align 4
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ret void
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}
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; 16: cmpi ${{[0-9]+}}, 10
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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