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b6a12c439f
This is almost the same as an existing IR canonicalization in instcombine, so I'm assuming this is a good early generic DAG combine too. The motivation comes from reduced bit-hacking for select-of-constants in IR after rL331486. We want to restore that functionality in the DAG as noted in the commit comments for that change and the llvm-dev discussion here: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html The PPC and AArch tests show that those targets are already doing something similar. x86 will be neutral in the minimal case and generally better when this pattern is extended with other ops as shown in the signbit-shift.ll tests. Note the asymmetry: we don't include the (extend (ifneg X)) transform because it already exists in SimplifySelectCC(), and that is verified in the later unchanged tests in the signbit-shift.ll files. Without the 'not' op, the general transform to use a shift is always a win because that's a single instruction. Alive proofs: https://rise4fun.com/Alive/ysli Name: if pos, get -1 %c = icmp sgt i16 %x, -1 %r = sext i1 %c to i16 => %n = xor i16 %x, -1 %r = ashr i16 %n, 15 Name: if pos, get 1 %c = icmp sgt i16 %x, -1 %r = zext i1 %c to i16 => %n = xor i16 %x, -1 %r = lshr i16 %n, 15 Differential Revision: https://reviews.llvm.org/D48970 llvm-svn: 337130
78 lines
1.5 KiB
LLVM
78 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
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define i32 @ashr(i32 %a, i32 %b) nounwind {
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%1 = ashr i32 %a, %b
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ret i32 %1
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}
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; CHECK-LABEL: ashr:
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; CHECK-NEXT: ashr r0, r0, r1
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define i32 @ashri1(i32 %a) nounwind {
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%1 = ashr i32 %a, 24
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ret i32 %1
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}
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; CHECK-LABEL: ashri1:
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; CHECK-NEXT: ashr r0, r0, 24
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define i32 @ashri2(i32 %a) nounwind {
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%1 = ashr i32 %a, 31
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ret i32 %1
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}
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; CHECK-LABEL: ashri2:
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; CHECK-NEXT: ashr r0, r0, 32
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define i32 @f1(i32 %a) nounwind nounwind {
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%1 = icmp slt i32 %a, 0
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br i1 %1, label %less, label %not_less
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less:
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ret i32 10
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not_less:
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ret i32 17
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}
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; CHECK-LABEL: f1:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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define i32 @f2(i32 %a) nounwind {
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%1 = icmp sge i32 %a, 0
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br i1 %1, label %greater, label %not_greater
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greater:
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ret i32 10
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not_greater:
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ret i32 17
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}
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; CHECK-LABEL: f2:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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define i32 @f3(i32 %a) nounwind {
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%1 = icmp slt i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK-LABEL: f3:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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; CHECK-NEXT: ldc r0, 17
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; CHECK: ldc r0, 10
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define i32 @f4(i32 %a) nounwind {
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%1 = icmp sge i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK-LABEL: f4:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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; CHECK-NEXT: ldc r0, 10
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; CHECK: ldc r0, 17
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define i32 @f5(i32 %a) nounwind {
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%1 = icmp sge i32 %a, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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; CHECK-LABEL: f5:
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; CHECK-NEXT: not r0, r0
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; CHECK-NEXT: mkmsk r1, 5
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; CHECK-NEXT: shr r0, r0, r1
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