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9d15235178
1. Deine FeatureRelax to enable/disable linker relaxation. 2. Define shouldForceRelocation to preserve relocation types even if the fixup can be resolved when linker relaxation enabled. This is necessary for correctness as offsets may change during relaxation. Differential Revision: https://reviews.llvm.org/D46674 llvm-svn: 332318
101 lines
3.6 KiB
TableGen
101 lines
3.6 KiB
TableGen
//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<"FeatureStdExtM">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<"FeatureStdExtA">;
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def FeatureStdExtF
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: SubtargetFeature<"f", "HasStdExtF", "true",
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"'F' (Single-Precision Floating-Point)">;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<"FeatureStdExtF">;
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def FeatureStdExtD
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: SubtargetFeature<"d", "HasStdExtD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
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AssemblerPredicate<"FeatureStdExtD">;
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def FeatureStdExtC
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: SubtargetFeature<"c", "HasStdExtC", "true",
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"'C' (Compressed Instructions)">;
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<"FeatureStdExtC">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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def IsRV64 : Predicate<"Subtarget->is64Bit()">,
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AssemblerPredicate<"Feature64Bit">;
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def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
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AssemblerPredicate<"!Feature64Bit">;
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def RV64 : HwMode<"+64bit">;
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def RV32 : HwMode<"-64bit">;
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def FeatureRelax
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: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
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"Enable Linker relaxation.">;
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//===----------------------------------------------------------------------===//
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// Registers, calling conventions, instruction descriptions.
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//===----------------------------------------------------------------------===//
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include "RISCVRegisterInfo.td"
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include "RISCVCallingConv.td"
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include "RISCVInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//
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def RISCVInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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}
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def RISCVAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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let AllowDuplicateRegisterNames = 1;
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}
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def RISCVAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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let AssemblyParsers = [RISCVAsmParser];
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let AssemblyWriters = [RISCVAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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