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llvm-mirror/lib/Target/RISCV/RISCV.td

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[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
//===----------------------------------------------------------------------===//
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
[RISCV] MC layer support for the standard RV32A instruction set extension llvm-svn: 317791
2017-11-09 16:00:03 +01:00
def FeatureStdExtM
: SubtargetFeature<"m", "HasStdExtM", "true",
"'M' (Integer Multiplication and Division)">;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
[RISCV] MC layer support for the standard RV32M instruction set extension llvm-svn: 317788
2017-11-09 15:46:30 +01:00
AssemblerPredicate<"FeatureStdExtM">;
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
[RISCV] MC layer support for the standard RV32A instruction set extension llvm-svn: 317791
2017-11-09 16:00:03 +01:00
def FeatureStdExtA
: SubtargetFeature<"a", "HasStdExtA", "true",
"'A' (Atomic Instructions)">;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<"FeatureStdExtA">;
[RISCV] MC layer support for the standard RV32F instruction set extension The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
2017-12-07 11:26:05 +01:00
def FeatureStdExtF
: SubtargetFeature<"f", "HasStdExtF", "true",
"'F' (Single-Precision Floating-Point)">;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<"FeatureStdExtF">;
[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
2017-12-07 11:46:23 +01:00
def FeatureStdExtD
: SubtargetFeature<"d", "HasStdExtD", "true",
"'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<"FeatureStdExtD">;
[RISCV] MC layer support for load/store instructions of the C (compressed) extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
2017-12-07 13:50:32 +01:00
def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true",
"'C' (Compressed Instructions)">;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<"FeatureStdExtC">;
[RISCV] MC layer support for the standard RV32A instruction set extension llvm-svn: 317791
2017-11-09 16:00:03 +01:00
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
[RISCV] MC layer support for the standard RV64I instructions llvm-svn: 320024
2017-12-07 11:53:48 +01:00
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<"Feature64Bit">;
[RISCV] Implement assembler pseudo instructions for RV32I and RV64I Adds the assembler pseudo instructions of RV32I and RV64I which can be mapped to a single canonical instruction. The missing pseudo instructions (e.g., call, tail, ...) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. Currently, alias emission is disabled by default to keep the patch minimal. Alias emission by default will be enabled in a subsequent patch which also updates all affected tests. Note that this patch should actually break the floating point MC tests. However, the used FileCheck configuration is not tight enought to detect the breakage. Differential Revision: https://reviews.llvm.org/D40902 Patch by Mario Werner. llvm-svn: 320487
2017-12-12 16:46:15 +01:00
def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Feature64Bit">;
[RISCV] MC layer support for the standard RV32M instruction set extension llvm-svn: 317788
2017-11-09 15:46:30 +01:00
def RV64 : HwMode<"+64bit">;
def RV32 : HwMode<"-64bit">;
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation 1. Deine FeatureRelax to enable/disable linker relaxation. 2. Define shouldForceRelocation to preserve relocation types even if the fixup can be resolved when linker relaxation enabled. This is necessary for correctness as offsets may change during relaxation. Differential Revision: https://reviews.llvm.org/D46674 llvm-svn: 332318
2018-05-15 03:28:50 +02:00
def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
//===----------------------------------------------------------------------===//
[RISCV] Initial codegen support for ALU operations This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
2017-10-19 23:37:38 +02:00
// Registers, calling conventions, instruction descriptions.
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
//===----------------------------------------------------------------------===//
include "RISCVRegisterInfo.td"
[RISCV] Initial codegen support for ALU operations This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
2017-10-19 23:37:38 +02:00
include "RISCVCallingConv.td"
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
include "RISCVInstrInfo.td"
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
//===----------------------------------------------------------------------===//
// Define the RISC-V target.
//===----------------------------------------------------------------------===//
[RISCV] Initial codegen support for ALU operations This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
2017-10-19 23:37:38 +02:00
def RISCVInstrInfo : InstrInfo {
[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0 rL162640 introduced CodeGenTarget::guessInstructionProperties. If a target sets guessInstructionProperties=0 in its FooInstrInfo, tablegen will error if it has to guess properties from patterns. Unfortunately, guessInstructionProperties=0 can't be used with current upstream LLVM as instructions in the TargetOpcode namespace are always included and sometimes have inferred properties for mayLoad, mayStore, and hasSideEffects. This patch provides the simplest possible fix to this problem, setting default values for these fields in the TargetOpcode scope. There is no intended functional change, as the explicitly set properties should match what was previously inferred. A number of the instructions had hasSideEffects=1 inferred unintentionally. This patch makes it explicit, while future patches (such as D37097) correct the property. Differential Revision: https://reviews.llvm.org/D37065 llvm-svn: 317674
2017-11-08 10:26:06 +01:00
let guessInstructionProperties = 0;
[RISCV] Initial codegen support for ALU operations This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
2017-10-19 23:37:38 +02:00
}
[RISCV] Prepare for the use of variable-sized register classes While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159
2017-10-19 16:29:03 +02:00
[RISCV] Add basic RISCVAsmParser This doesn't yet support parsing things like %pcrel_hi(foo), but will handle basic instructions with register or immediate operands. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310361
2017-08-08 16:32:35 +02:00
def RISCVAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = 1;
[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
2017-12-07 11:46:23 +01:00
let AllowDuplicateRegisterNames = 1;
[RISCV] Add basic RISCVAsmParser This doesn't yet support parsing things like %pcrel_hi(foo), but will handle basic instructions with register or immediate operands. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310361
2017-08-08 16:32:35 +02:00
}
[RISCV] Pass MCSubtargetInfo to print methods. Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
2018-01-12 03:27:00 +01:00
def RISCVAsmWriter : AsmWriter {
int PassSubtarget = 1;
}
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
[RISCV] Add basic RISCVAsmParser This doesn't yet support parsing things like %pcrel_hi(foo), but will handle basic instructions with register or immediate operands. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310361
2017-08-08 16:32:35 +02:00
let AssemblyParsers = [RISCVAsmParser];
[RISCV] Pass MCSubtargetInfo to print methods. Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
2018-01-12 03:27:00 +01:00
let AssemblyWriters = [RISCVAsmWriter];
[MachineOperand][Target] MachineOperand::isRenamable semantics changes Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
2018-02-23 19:25:08 +01:00
let AllowRegisterRenaming = 1;
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
2016-11-02 00:40:28 +01:00
}
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