Artem Belevich 848056d8ad [NVPTX] Implemented wmma intrinsics and instructions. ... WMMA = "Warp Level Matrix Multiply-Accumulate". These are the new instructions introduced in PTX6.0 and available on sm_70 GPUs. Differential Revision: https://reviews.llvm.org/D38645 llvm-svn: 315601		2017-10-12 18:27:55 +00:00
..
access-non-generic.ll
add-128bit.ll
addrspacecast-gvar.ll
addrspacecast.ll
aggr-param.ll
aggregate-return.ll
alias.ll
annotations.ll
arg-lowering.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
atomics-with-scope.ll
atomics.ll
barrier.ll	[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.	2017-09-21 18:44:49 +00:00
bfe.ll
branch-fold.ll
bug17709.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
bug21465.ll
bug22246.ll
bug22322.ll
bug26185-2.ll
bug26185.ll
bypass-div.ll
call-with-alloca-buffer.ll
callchain.ll
calling-conv.ll
combine-min-max.ll
compare-int.ll
constant-vectors.ll
convergent-mir-call.ll
convert-fp.ll
convert-int-sm20.ll
ctlz.ll	[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)	2017-05-12 19:56:43 +00:00
ctpop.ll	[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)	2017-05-12 19:56:43 +00:00
cttz.ll	[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)	2017-05-12 19:56:43 +00:00
debug-file-loc.ll
disable-opt.ll
div-ri.ll
divrem-combine.ll
envreg.ll
extloadv.ll
f16-instructions.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
f16x2-instructions.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
fast-math.ll
fcos-no-fast-math.ll
fma-assoc.ll
fma-disable.ll
fma.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
fp16.ll
fp-contract.ll
fp-literals.ll
fsin-no-fast-math.ll
function-align.ll
generic-to-nvvm-ir.ll	Canonicalize the representation of empty an expression in DIGlobalVariableExpression	2017-08-30 18:06:51 +00:00
generic-to-nvvm.ll
global-addrspace.ll
global-ctor-empty.ll
global-ctor.ll
global-dtor.ll
global-ordering.ll
global-variable-big.ll
global-visibility.ll
globals_init.ll
globals_lowering.ll
gvar-init.ll
half.ll
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
i128-global.ll	[NVPTX] Add lowering of i128 params.	2017-07-20 21:16:03 +00:00
i128-param.ll	[NVPTX] Add lowering of i128 params.	2017-07-20 21:16:03 +00:00
i128-retval.ll	[NVPTX] Add lowering of i128 params.	2017-07-20 21:16:03 +00:00
idioms.ll
imad.ll
implicit-def.ll
inline-asm.ll
intrin-nocapture.ll
intrinsic-old.ll
intrinsics.ll
isspacep.ll
ld-addrspace.ll
ld-generic.ll
ldg-invariant.ll
ldparam-v4.ll
ldu-i8.ll
ldu-ldg.ll
ldu-reg-plus-offset.ll
lit.local.cfg
load-sext-i1.ll
load-with-non-coherent-cache.ll
LoadStoreVectorizer.ll
local-stack-frame.ll
loop-vectorize.ll
lower-aggr-copies.ll	Extend memcpy expansion in Transform/Utils to handle wider operand types.	2017-07-07 02:00:06 +00:00
lower-alloca.ll
lower-kernel-ptr-arg.ll
machine-sink.ll
MachineSink-call.ll
MachineSink-convergent.ll
managed.ll
match.ll	[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.	2017-09-26 17:07:23 +00:00
math-intrins.ll
misaligned-vector-ldst.ll
module-inline-asm.ll
mulwide.ll
named-barriers.ll
noduplicate-syncthreads.ll
nounroll.ll
nvcl-param-align.ll
nvvm-reflect-module-flag.ll
nvvm-reflect.ll
param-align.ll
param-load-store.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
pr13291-i1-store.ll
pr16278.ll
pr17529.ll
refl1.ll
reg-copy.ll
reg-types.ll
rotate.ll
sched1.ll	Only enable LiveRangeShrink for x86.	2017-05-17 20:18:13 +00:00
sched2.ll	Only enable LiveRangeShrink for x86.	2017-05-17 20:18:13 +00:00
sext-in-reg.ll
sext-params.ll
shfl-sync.ll	[NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.	2017-09-20 21:23:07 +00:00
shfl.ll
shift-parts.ll
simple-call.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-32.ll
sm-version-35.ll
sm-version-37.ll
sm-version-50.ll
sm-version-52.ll
sm-version-53.ll
sm-version-60.ll
sm-version-61.ll
sm-version-62.ll
sm-version-70.ll	[CUDA] Added rudimentary support for CUDA-9 and sm_70.	2017-09-07 18:14:32 +00:00
speculative-execution-divergent-target.ll
sqrt-approx.ll
st-addrspace.ll
st-generic.ll
surf-read-cuda.ll
surf-read.ll
surf-write-cuda.ll
surf-write.ll
symbol-naming.ll
TailDuplication-convergent.ll
tex-read-cuda.ll
tex-read.ll
texsurf-queries.ll
tid-range.ll
tuple-literal.ll
vec8.ll	Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."	2017-05-18 18:50:05 +00:00
vec-param-load.ll
vector-args.ll
vector-call.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00
vector-compare.ll
vector-global.ll
vector-loads.ll
vector-select.ll
vector-stores.ll
vote.ll	[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.	2017-09-21 18:44:49 +00:00
weak-global.ll
weak-linkage.ll
wmma.py	[NVPTX] Implemented wmma intrinsics and instructions.	2017-10-12 18:27:55 +00:00
zero-cs.ll
zeroext-32bit.ll	[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)	2017-05-15 17:17:44 +00:00