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https://github.com/RPCS3/llvm-mirror.git
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a03ce058a1
AArch64, X86 and Mips currently directly consumes these and custom lowering to produce a libcall, but really these should follow the normal legalization process through the libcall/lower action.
171 lines
6.2 KiB
YAML
171 lines
6.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_memcpy
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memcpy
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: $x1 = COPY [[COPY1]](p0)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 0 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memcpy_tail
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memcpy_tail
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: $x1 = COPY [[COPY1]](p0)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: TCRETURNdi &memcpy, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memmove
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: test_memmove
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: $x1 = COPY [[COPY1]](p0)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: BL &memmove, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMMOVE %0(p0), %1(p0), %3(s64), 0 :: (store unknown-size), (load unknown-size)
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RET_ReallyLR
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...
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---
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name: test_memset
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w1, $w2, $x0
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; CHECK-LABEL: name: test_memset
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; CHECK: liveins: $w1, $w2, $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: $w1 = COPY [[COPY3]](s32)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: BL &memset, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%1:_(s32) = COPY $w1
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%2:_(s32) = COPY $w2
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%3:_(s8) = G_TRUNC %1(s32)
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%4:_(s64) = G_ZEXT %2(s32)
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G_MEMSET %0(p0), %3(s8), %4(s64), 0 :: (store unknown-size)
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RET_ReallyLR
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...
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---
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name: no_tail_call
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: no_tail_call
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: $x1 = COPY [[COPY1]](p0)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[ZEXT]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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$x0 = COPY %3
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_tc_twice
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w2, $x0, $x1
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; CHECK-LABEL: name: dont_tc_twice
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; CHECK: liveins: $w2, $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $x0 = COPY [[COPY]](p0)
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; CHECK: $x1 = COPY [[COPY1]](p0)
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; CHECK: $x2 = COPY [[ZEXT]](s64)
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; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(s32) = COPY $w2
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%4:_(s1) = G_CONSTANT i1 false
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%3:_(s64) = G_ZEXT %2(s32)
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G_MEMCPY %0(p0), %1(p0), %3(s64), 1 :: (store unknown-size), (load unknown-size)
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TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp
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