mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
8a964bb5a4
Previously for any copy from a register bigger than the destination: Copied to a same-sized register in the destination register bank. Subregister copy of that to the destination. This fails for copies from 128-bit FPRs to GPRs because the GPR register bank can't accomodate 128-bit values. Instead of special-casing such copies to perform the truncation beforehand in the source register bank, generalize this: a) Perform a subregister copy straight from source register whenever possible. This results in shorter MIR and fixes the above problem. b) Perform a full copy to target bank and then do a subregister copy only if source bank can't support target's size. E.g. GPR to 8-bit FPR copy. Patch by Raul Tambre (tambre)! Differential Revision: https://reviews.llvm.org/D75421
431 lines
12 KiB
YAML
431 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: shl_gep_sext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with two 1s, representing a shift
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; plus sign extend.
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; CHECK-LABEL: name: shl_gep_sext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 1, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 2
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%offset:gpr(s64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_gep_zext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with a 0 representing a zero-extend
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; and a 1 representing a shift.
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; CHECK-LABEL: name: shl_gep_zext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_ZEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 2
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%offset:gpr(s64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_gep_anyext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to fold a shift + extend into the pattern.
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; In this case, we should get a roW load with a 0 representing a zero-extend
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; and a 1 representing a shift.
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; CHECK-LABEL: name: shl_gep_anyext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_ANYEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 2
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%offset:gpr(s64) = G_SHL %ext, %c
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_sext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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; We should be able to do the same with multiplies as with shifts.
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liveins: $w1, $x0
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; CHECK-LABEL: name: mul_gep_sext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 1, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 4
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_zext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to do the same with multiplies as with shifts.
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; CHECK-LABEL: name: mul_gep_zext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_ZEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 4
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: mul_gep_anyext_ldrwrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0
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; We should be able to do the same with multiplies as with shifts.
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; CHECK-LABEL: name: mul_gep_anyext_ldrwrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr32 = LDRWroW %base, %foo, 0, 1 :: (load 4)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_ANYEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 4
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ldrdrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0, $d0
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; Verify that we can select LDRDroW.
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; CHECK-LABEL: name: ldrdrow
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; CHECK: liveins: $w1, $x0, $d0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:fpr64 = LDRDroW %base, %foo, 1, 1 :: (load 8)
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; CHECK: $x0 = COPY %load
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; CHECK: RET_ReallyLR implicit $x0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 8
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:fpr(<2 x s32>) = G_LOAD %ptr(p0) :: (load 8)
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$x0 = COPY %load(<2 x s32>)
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RET_ReallyLR implicit $x0
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...
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---
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name: ldrxrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w1, $x0, $d0
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; Verify that we can select LDRXroW.
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; CHECK-LABEL: name: ldrxrow
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; CHECK: liveins: $w1, $x0, $d0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:gpr64 = LDRXroW %base, %foo, 1, 1 :: (load 8)
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; CHECK: $x0 = COPY %load
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; CHECK: RET_ReallyLR implicit $x0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 8
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
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$x0 = COPY %load(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: ldrbbrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $x0, $w0, $w1
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; Verify that we can select LDRBBroW. Note that there is no shift here,
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; but we still fold the extend into the addressing mode.
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; CHECK-LABEL: name: ldrbbrow
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; CHECK: liveins: $x0, $w0, $w1
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; CHECK: %val:gpr32 = COPY $w1
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %load:gpr32 = LDRBBroW %base, %val, 1, 0 :: (load 1)
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; CHECK: $w0 = COPY %load
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; CHECK: RET_ReallyLR implicit $w0
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%val:gpr(s32) = COPY $w1
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%base:gpr(p0) = COPY $x0
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%ext:gpr(s64) = G_SEXT %val(s32)
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%ptr:gpr(p0) = G_PTR_ADD %base, %ext(s64)
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%load:gpr(s32) = G_LOAD %ptr(p0) :: (load 1)
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$w0 = COPY %load(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ldrhrow
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $w1, $x0
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; Verify that we can select ldrhrow.
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; CHECK-LABEL: name: ldrhrow
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; CHECK: liveins: $w1, $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %foo:gpr32 = COPY $w1
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; CHECK: %load:fpr16 = LDRHroW %base, %foo, 1, 1 :: (load 2)
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; CHECK: $h0 = COPY %load
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; CHECK: RET_ReallyLR implicit $h0
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%base:gpr(p0) = COPY $x0
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%foo:gpr(s32) = COPY $w1
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%ext:gpr(s64) = G_SEXT %foo(s32)
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%c:gpr(s64) = G_CONSTANT i64 2
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%offset:gpr(s64) = G_MUL %c, %ext
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%ptr:gpr(p0) = G_PTR_ADD %base, %offset(s64)
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%load:fpr(s16) = G_LOAD %ptr(p0) :: (load 2)
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$h0 = COPY %load(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: bad_and_mask_1
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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bb.0:
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liveins: $x0
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; We should get a roX load here, not a roW load. We can't use the mask in
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; this test for an extend.
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; CHECK-LABEL: name: bad_and_mask_1
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; CHECK: liveins: $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %imp:gpr64 = IMPLICIT_DEF
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; CHECK: %and:gpr64common = ANDXri %imp, 4103
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; CHECK: %load:gpr64 = LDRXroX %base, %and, 0, 1 :: (load 8)
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; CHECK: $x1 = COPY %load
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; CHECK: RET_ReallyLR implicit $x1
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%base:gpr(p0) = COPY $x0
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%imp:gpr(s64) = G_IMPLICIT_DEF
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%bad_mask:gpr(s64) = G_CONSTANT i64 255
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%and:gpr(s64) = G_AND %imp, %bad_mask
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%c:gpr(s64) = G_CONSTANT i64 8
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%mul:gpr(s64) = G_MUL %c, %and
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%ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
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$x1 = COPY %load(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: bad_and_mask_2
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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bb.0:
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liveins: $x0
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; We should get a roX load here, not a roW load. We can't use the mask in
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; this test for an extend.
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; CHECK-LABEL: name: bad_and_mask_2
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; CHECK: liveins: $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %imp:gpr64 = IMPLICIT_DEF
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; CHECK: %and:gpr64common = ANDXri %imp, 4111
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; CHECK: %load:gpr64 = LDRXroX %base, %and, 0, 1 :: (load 8)
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; CHECK: $x1 = COPY %load
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; CHECK: RET_ReallyLR implicit $x1
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%base:gpr(p0) = COPY $x0
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%imp:gpr(s64) = G_IMPLICIT_DEF
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%bad_mask:gpr(s64) = G_CONSTANT i64 65535
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%and:gpr(s64) = G_AND %imp, %bad_mask
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%c:gpr(s64) = G_CONSTANT i64 8
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%mul:gpr(s64) = G_MUL %c, %and
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%ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
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$x1 = COPY %load(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: and_uxtw
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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bb.0:
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liveins: $x0
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; The mask used for the AND here is legal for producing a roW load.
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; CHECK-LABEL: name: and_uxtw
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; CHECK: liveins: $x0
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; CHECK: %base:gpr64sp = COPY $x0
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; CHECK: %imp:gpr64 = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %imp.sub_32
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: %load:gpr64 = LDRXroW %base, [[COPY1]], 0, 1 :: (load 8)
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; CHECK: $x1 = COPY %load
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; CHECK: RET_ReallyLR implicit $x1
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%base:gpr(p0) = COPY $x0
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%imp:gpr(s64) = G_IMPLICIT_DEF
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%mask:gpr(s64) = G_CONSTANT i64 4294967295
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%and:gpr(s64) = G_AND %imp, %mask
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%c:gpr(s64) = G_CONSTANT i64 8
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%mul:gpr(s64) = G_MUL %c, %and
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%ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
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%load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
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$x1 = COPY %load(s64)
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RET_ReallyLR implicit $x1
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...
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