mirror of
https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
212 lines
5.9 KiB
YAML
212 lines
5.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: v2s32_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
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; CHECK: $s0 = COPY [[CPYi32_]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s32>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s32_fpr_idx0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32_fpr_idx0
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK: $s0 = COPY [[COPY1]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s32>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 0
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s64_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 2
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; CHECK: $d0 = COPY [[CPYi64_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s64>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 2
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s16_fpr
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<4 x s16>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_zext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_zext
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s64) = G_ZEXT %1
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%3:fpr(s64) = COPY %2(s64)
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%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %4(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_sext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_sext
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s64) = G_SEXT %1
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%3:fpr(s64) = COPY %2(s64)
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%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %4(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_trunc
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_trunc
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
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; CHECK: $h0 = COPY [[CPYi16_]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s32) = G_TRUNC %1
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%3:gpr(s64) = G_SEXT %2
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%4:fpr(s64) = COPY %3(s64)
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%5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
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$h0 = COPY %5(s16)
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RET_ReallyLR implicit $h0
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