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llvm-mirror/test/CodeGen/AArch64/arm64_32-tls.ll
Tim Northover 1bb14916f2 AArch64: support arm64_32, an ILP32 slice for watchOS.
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM.
FastISel is mostly disabled for now since it would generate incorrect code for
ILP32.

llvm-svn: 371722
2019-09-12 10:22:23 +00:00

23 lines
550 B
LLVM

; RUN: llc -mtriple=arm64_32-apple-ios %s -o - | FileCheck %s
define i32 @test_thread_local() {
; CHECK-LABEL: test_thread_local:
; CHECK: adrp x[[TMP:[0-9]+]], _var@TLVPPAGE
; CHECK: ldr w0, [x[[TMP]], _var@TLVPPAGEOFF]
; CHECK: ldr w[[DEST:[0-9]+]], [x0]
; CHECK: blr x[[DEST]]
%val = load i32, i32* @var
ret i32 %val
}
@var = thread_local global i32 zeroinitializer
; CHECK: .tbss _var$tlv$init, 4, 2
; CHECK-LABEL: __DATA,__thread_vars
; CHECK: _var:
; CHECK: .long __tlv_bootstrap
; CHECK: .long 0
; CHECK: .long _var$tlv$init