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828720bb36
We have found that -- when the selected subarchitecture has a scheduling model and we are not optimizing for size -- the machine-instruction combiner uses a too-simple algorithm to compute the cost of one of the two alternatives [before and after running a combining pass on a section of code], and therefor it throws away the combination results too often. This fix has the potential to help any ISA with the potential to combine instructions and for which at least one subarchitecture has a scheduling model. As of now, this is only known to definitely affect AArch64 subarchitectures with a scheduling model. Regression tested on AMD64/GNU-Linux, new test case tested to fail on an unpatched compiler and pass on a patched compiler. Patch by Abe Skolnik and Sebastian Pop. llvm-svn: 289399
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios7.0 -mcpu=cyclone %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64_be-linux-gnu -mcpu=cyclone %s -o - | FileCheck --check-prefix=CHECK-BE %s
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define i128 @test_128bitmul(i128 %lhs, i128 %rhs) {
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; CHECK-LABEL: test_128bitmul:
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; CHECK: umulh [[HI:x[0-9]+]], x0, x2
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; CHECK: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
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; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
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; CHECK-DAG: mul x0, x0, x2
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; CHECK-NEXT: ret
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; CHECK-BE-LABEL: test_128bitmul:
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; CHECK-BE: umulh [[HI:x[0-9]+]], x1, x3
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; CHECK-BE: madd [[TEMP1:x[0-9]+]], x1, x2, [[HI]]
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; CHECK-BE-DAG: madd x0, x0, x3, [[TEMP1]]
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; CHECK-BE-DAG: mul x1, x1, x3
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; CHECK-BE-NEXT: ret
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%prod = mul i128 %lhs, %rhs
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ret i128 %prod
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}
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; The machine combiner should create madd instructions when
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; optimizing for size because that's smaller than mul + add.
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define i128 @test_128bitmul_optsize(i128 %lhs, i128 %rhs) optsize {
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; CHECK-LABEL: test_128bitmul_optsize:
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; CHECK: umulh [[HI:x[0-9]+]], x0, x2
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; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
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; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
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; CHECK-DAG: mul x0, x0, x2
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; CHECK-NEXT: ret
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%prod = mul i128 %lhs, %rhs
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ret i128 %prod
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}
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define i128 @test_128bitmul_minsize(i128 %lhs, i128 %rhs) minsize {
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; CHECK-LABEL: test_128bitmul_minsize:
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; CHECK: umulh [[HI:x[0-9]+]], x0, x2
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; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
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; CHECK-DAG: madd x1, x1, x2, [[TEMP1]]
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; CHECK-DAG: mul x0, x0, x2
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; CHECK-NEXT: ret
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%prod = mul i128 %lhs, %rhs
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ret i128 %prod
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}
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