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https://github.com/RPCS3/llvm-mirror.git
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a0ef9a3456
This is exchanging a sub-of-1 with add-of-minus-1: https://rise4fun.com/Alive/plKAH This is another step towards improving select-of-constants codegen (see D48970). x86 is the motivating target, and those diffs all appear to be wins. PPC and AArch64 look neutral. I've limited this to early combining (!LegalOperations) in case a target wants to reverse it, but I think canonicalizing to 'add' is more likely to produce further transforms because we have more folds for 'add'. Differential Revision: https://reviews.llvm.org/D49924 llvm-svn: 338317
269 lines
6.8 KiB
LLVM
269 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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; If positive...
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define i32 @zext_ifpos(i32 %x) {
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; CHECK-LABEL: zext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: lsr w0, w8, #31
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_zext_ifpos(i32 %x) {
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; CHECK-LABEL: add_zext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #42 // =42
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_zext_ifpos_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #41
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = zext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_tval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, ge
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifpos(i32 %x) {
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; CHECK-LABEL: sext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: asr w0, w8, #31
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_sext_ifpos(i32 %x) {
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; CHECK-LABEL: add_sext_ifpos:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #41 // =41
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_sext_ifpos_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = sext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_fval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, lt
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; CHECK-NEXT: ret
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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; If negative...
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define i32 @zext_ifneg(i32 %x) {
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; CHECK-LABEL: zext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w0, w0, #31
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_zext_ifneg(i32 %x) {
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; CHECK-LABEL: add_zext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #41 // =41
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define i32 @sel_ifneg_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_tval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, lt
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifneg(i32 %x) {
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; CHECK-LABEL: sext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w0, w0, #31
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = sext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_sext_ifneg(i32 %x) {
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; CHECK-LABEL: add_sext_ifneg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #42 // =42
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define i32 @sel_ifneg_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_fval_bigger:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #0 // =0
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; CHECK-NEXT: mov w8, #41
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; CHECK-NEXT: cinc w0, w8, ge
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; CHECK-NEXT: ret
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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define i32 @add_lshr_not(i32 %x) {
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; CHECK-LABEL: add_lshr_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #42 // =42
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; CHECK-NEXT: ret
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = add i32 %sh, 41
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ret i32 %r
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}
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #43
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; CHECK-NEXT: ssra v1.4s, v0.4s, #31
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sub_lshr_not(i32 %x) {
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; CHECK-LABEL: sub_lshr_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #42
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; CHECK-NEXT: bfxil w8, w0, #31, #1
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: ret
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #41
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; CHECK-NEXT: usra v1.4s, v0.4s, #31
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
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ret <4 x i32> %r
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}
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define i32 @sub_lshr(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w0, w1, w0, asr #31
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; CHECK-NEXT: ret
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%sh = lshr i32 %x, 31
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%r = sub i32 %y, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: sub_lshr_vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ssra v1.4s, v0.4s, #31
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> %y, %sh
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ret <4 x i32> %r
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}
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define i32 @sub_const_op_lshr(i32 %x) {
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; CHECK-LABEL: sub_const_op_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr w8, w0, #31
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; CHECK-NEXT: add w0, w8, #43 // =43
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; CHECK-NEXT: ret
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%sh = lshr i32 %x, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
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; CHECK-LABEL: sub_const_op_lshr_vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: ssra v1.4s, v0.4s, #31
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
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ret <4 x i32> %r
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}
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