Thomas Lively 30f77c8929 [WebAssembly] SIMD shifts ... Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302		2018-09-15 00:45:31 +00:00
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AArch64	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AMDGPU	AMDGPU: Print all kernel descriptor directives (including the ones with default values)	2018-09-12 20:25:39 +00:00
ARM	[DWARF] reposting r342048, which was reverted in r342056 due to buildbot	2018-09-14 09:14:10 +00:00
AsmParser	[debuginfo] generate debug info with asm+.file	2018-08-28 16:23:39 +00:00
AVR	[AVR] Redefine the 'SBR' instruction as an alias	2018-09-01 12:22:54 +00:00
BPF	bpf: New disassembler testcases for 32-bit subregister support	2018-02-23 23:49:35 +00:00
COFF	[codeview] Add .cv_string directive for testing purposes	2018-09-07 21:30:52 +00:00
Disassembler	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
ELF	The initial .text section generated in object files was missing the	2018-09-06 22:09:31 +00:00
Hexagon	Check for tied operands	2018-08-13 14:01:25 +00:00
Lanai
MachO	[MC/Dwarf] Unclamp DWARF linetables format on Darwin.	2018-09-13 13:13:50 +00:00
Mips	[mips] Enable the mnemonic spell corrector	2018-09-13 08:38:03 +00:00
PowerPC	[PowerPC][MC] Support expressions in getMemRIX16Encoding.	2018-08-27 17:37:43 +00:00
RISCV	[RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types	2018-09-13 18:37:23 +00:00
Sparc	[Sparc] allow tls_add/tls_call syntax in assembler parser	2018-09-03 10:38:12 +00:00
SystemZ
WebAssembly	[WebAssembly] SIMD shifts	2018-09-15 00:45:31 +00:00
X86	[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.	2018-09-06 02:03:14 +00:00