Ana Pazos d1818e7c07 [RISCV] Fix decoding of invalid instruction with C extension enabled. ... Summary: The illegal instruction 0x00 0x00 is being wrongly decoded as c.addi4spn with 0 immediate. The invalid instruction 0x01 0x61 is being wrongly decoded as c.addi16sp with 0 immediate. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51815 llvm-svn: 342159		2018-09-13 18:21:19 +00:00
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AArch64	[ARM/AArch64] Support FP16 +fp16fml instructions	2018-08-17 11:29:49 +00:00
AMDGPU	AMDGPU: Fix v_dot{4, 8}* instruction encoding	2018-05-15 19:32:47 +00:00
ARC	[ARC] Prevent InstPrinter from crashing on unknown condition codes.	2018-09-06 19:58:26 +00:00
ARM	[ARM/AArch64] Support FP16 +fp16fml instructions	2018-08-17 11:29:49 +00:00
Hexagon	NFC - Various typo fixes in tests	2018-07-04 13:28:39 +00:00
Lanai
Mips	[mips] Add missing instructions	2018-08-29 11:35:03 +00:00
PowerPC	Complete the SPE instruction set patterns	2018-07-18 04:24:57 +00:00
RISCV	[RISCV] Fix decoding of invalid instruction with C extension enabled.	2018-09-13 18:21:19 +00:00
Sparc
SystemZ
WebAssembly	[WebAssembly] v8x16.shuffle	2018-09-07 21:54:46 +00:00
X86	[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.	2018-08-13 22:06:28 +00:00
XCore