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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
152 lines
5.2 KiB
YAML
152 lines
5.2 KiB
YAML
# RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m--none-eabi"
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declare void @exit0()
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declare void @exit1(i32)
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declare void @exit2()
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declare void @exit3()
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declare void @exit4()
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define void @jump_table(i32 %val, i32 %arg2, i32 %arg3, i32 %arg4) {
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entry:
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switch i32 %val, label %default [
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i32 1, label %lab1
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i32 2, label %lab2
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i32 3, label %lab3
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i32 4, label %lab4
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]
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default: ; preds = %entry
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tail call void @exit0()
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ret void
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lab1: ; preds = %entry
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%b = sub i32 %val, 1
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%a = shl i32 %b, 2
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tail call void @exit1(i32 %a)
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ret void
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lab2: ; preds = %entry
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tail call void @exit2()
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ret void
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lab3: ; preds = %entry
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tail call void @exit3()
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ret void
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lab4: ; preds = %entry
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tail call void @exit4()
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #0
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attributes #0 = { nounwind }
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...
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---
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name: jump_table
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0' }
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calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
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'$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
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'$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
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'$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
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'$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
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'$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
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'$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
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'$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
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'$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
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'$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
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'$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
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'$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
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'$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
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'$d11_d12_d13_d14' ]
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
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- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
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jumpTable:
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kind: inline
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entries:
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- id: 0
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blocks: [ '%bb.3.lab1', '%bb.4.lab2', '%bb.5.lab3', '%bb.6.lab4' ]
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# r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered!
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# CHECK-NOT: tTBB_JT
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body: |
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bb.0.entry:
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successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668)
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liveins: $r0, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r1, dead $cpsr = tSUBi3 $r0, 1, 14, $noreg
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tCMPi8 $r1, 3, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2.default, 8, killed $cpsr
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bb.1.entry:
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successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000)
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liveins: $r0, $r1
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$r1, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
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$r2 = tLEApcrelJT %jump-table.0, 14, $noreg
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$r2 = tLDRr killed $r1, killed $r2, 14, $noreg :: (load 4 from jump-table)
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$r1, dead $cpsr = tLSLri $r2, 2, 14, $noreg
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tBR_JTr killed $r2, %jump-table.0
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bb.2.default:
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tBL 14, $noreg, @exit0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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bb.3.lab1:
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liveins: $r0,$r1
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tBL 14, $noreg, @exit1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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bb.4.lab2:
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tBL 14, $noreg, @exit2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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bb.5.lab3:
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tBL 14, $noreg, @exit3, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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bb.6.lab4:
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tBL 14, $noreg, @exit4, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit-def $sp, implicit $sp
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...
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