Craig Topper 1e7d252842 [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs ... Now that we legalize by widening, the element types here won't change. Previously these were modeled as the elements being widened and then the instruction might become an AND or SHL/ASHR pair. But now they'll become something like a ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG. For AVX2, when the destination type is legal its clear the cost should be 1 since we have extend instructions that can produce 256 bit vectors from less than 128 bit vectors. I'm a little less sure about AVX1 costs, but I think the ones I changed were definitely too high, but they might still be too high. Differential Revision: https://reviews.llvm.org/D66169 llvm-svn: 368858		2019-08-14 14:52:39 +00:00
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AArch64	[CostModel][X86][AArch64] Check all 3 cost kinds in aggregates.ll	2019-08-12 17:45:12 +00:00
AMDGPU	TTI: Improve default costs for addrspacecast	2019-06-03 18:41:34 +00:00
ARM	[ARM] Add MVE beats vector cost model	2019-08-13 18:12:08 +00:00
PowerPC	Revert Recommit [PowerPC] Update P9 vector costs for insert/extract element	2019-07-01 23:29:46 +00:00
RISCV	[lit] Delete empty lines at the end of lit.local.cfg NFC	2019-06-17 09:51:07 +00:00
SystemZ	[SystemZ] Add support for new cpu architecture - arch13	2019-07-12 18:13:16 +00:00
X86	[X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs	2019-08-14 14:52:39 +00:00
no_info.ll