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1e7d252842
llvm-mirror/test/Analysis/CostModel/X86
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Craig Topper 1e7d252842 [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs 
Now that we legalize by widening, the element types here won't change. Previously these were modeled as the elements being widened and then the instruction might become an AND or SHL/ASHR pair. But now they'll become something like a ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG.

For AVX2, when the destination type is legal its clear the cost should be 1 since we have extend instructions that can produce 256 bit vectors from less than 128 bit vectors. I'm a little less sure about AVX1 costs, but I think the ones I changed were definitely too high, but they might still be too high.

Differential Revision: https://reviews.llvm.org/D66169

llvm-svn: 368858
2019-08-14 14:52:39 +00:00
..
aggregates.ll [CostModel][X86][AArch64] Check all 3 cost kinds in aggregates.ll 2019-08-12 17:45:12 +00:00
alternate-shuffle-cost.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
arith-fix.ll [TTI] Add generic cost model for fixed point smul/umul 2019-02-25 11:59:23 +00:00
arith-fma.ll
arith-fp.ll [CostModel] Add really basic support for being able to query the cost of the FNeg instruction. 2019-05-28 04:09:18 +00:00
arith-overflow.ll [TTI] Add generic cost model for smul/umul overflow intrinsics 2019-02-25 13:30:23 +00:00
arith-ssat.ll [TTI] Add generic SADDSAT/SSUBSAT costs 2019-01-27 13:51:59 +00:00
arith-usat.ll [CodeGen][X86] Expand UADDSAT to NOT+UMIN+ADD 2019-01-28 19:19:09 +00:00
arith.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
bitreverse.ll
bswap.ll
cast.ll [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs 2019-08-14 14:52:39 +00:00
costmodel.ll
ctlz.ll
ctpop.ll
cttz.ll
div.ll
extend.ll [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs 2019-08-14 14:52:39 +00:00
fcmp.ll [CostModel][X86] Add explicit fcmp costs for pre-SSE42 targets 2019-01-20 13:21:43 +00:00
fptosi.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
fptoui.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
fround.ll
fshl.ll [CostModel][X86] Add explicit vector select costs 2019-01-20 13:55:01 +00:00
fshr.ll [CostModel][X86] Add explicit vector select costs 2019-01-20 13:55:01 +00:00
gep.ll
i32.ll
icmp.ll [CostModel][X86] Add ICMP Predicate specific costs 2019-01-22 12:29:38 +00:00
insert-extract-at-zero.ll
interleave-load-i32.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
interleave-store-i32.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
interleaved-load-float.ll
interleaved-load-i8.ll
interleaved-load-store-double.ll
interleaved-load-store-i64.ll
interleaved-store-i8.ll
intrinsic-cost.ll
lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
load_store.ll
loop_v2.ll
masked-intrinsic-cost.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
min-legal-vector-width.ll [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs 2019-08-14 14:52:39 +00:00
reduce-add.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-and.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-mul.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-or.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-smax.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-smin.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-umax.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-umin.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-xor.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduction.ll [CostModel][X86] Don't count 2 shuffles on the last level of a pairwise arithmetic or min/max reduction 2018-12-13 19:08:10 +00:00
rem.ll
scalarize.ll
shuffle-broadcast.ll
shuffle-extract_subvector.ll [X86] Add missing regular 512-bit vXi8 extract subvector cost model tests 2019-08-14 12:36:23 +00:00
shuffle-insert_subvector.ll
shuffle-reverse.ll
shuffle-single-src.ll
shuffle-transpose.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
shuffle-two-src.ll
sitofp.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
slm-arith-costs.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
sse-itoi.ll
strided-load-i8.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
strided-load-i16.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
strided-load-i32.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
strided-load-i64.ll [X86] Replace '-mcpu=skx' with -mattr=avx512f or -mattr=avx512bw in interleave/strided load/store cost model tests. 2018-12-01 00:21:49 +00:00
testshiftashr.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
testshiftlshr.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
testshiftshl.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
tiny.ll
trunc.ll [CostModel][X86] Add truncate cost tests to cover all legal destination types 2019-01-03 14:49:39 +00:00
uitofp.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
uniformshift.ll
vdiv-cost.ll
vector_gep.ll
vector-extract.ll
vector-insert.ll
vectorized-loop.ll
vselect-cost.ll [CostModel][X86] Add explicit vector select costs 2019-01-20 13:55:01 +00:00
vshift-ashr-cost.ll
vshift-lshr-cost.ll
vshift-shl-cost.ll