Saleem Abdulrasool 91b29d5518 ARM: maintain BB ordering when expanding WIN__DBZCHK ... It is possible to have a fallthrough MBB prior to MBB placement. The original addition of the BB would result in reordering the BB as not preceding the successor. Because of the fallthrough nature of the BB, we could end up executing incorrect code or even a constant pool island! Insert the spliced BB into the same location to avoid that. Thanks to Tim Northover for invaluable hints and Fiora for the discussion on what may have been occurring! llvm-svn: 264454		2016-03-25 19:48:06 +00:00
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AArch64	[CXX_FAST_TLS] Disable tail call when calling conventions are mismatched.	2016-03-18 23:41:51 +00:00
AMDGPU	LiveInterval: Fix Distribute() failing on liveranges with unused VNInfos	2016-03-24 21:41:38 +00:00
ARM	ARM: maintain BB ordering when expanding WIN__DBZCHK	2016-03-25 19:48:06 +00:00
BPF	BPF: emit an error message for unsupported signed division operation	2016-03-18 22:02:47 +00:00
CPP
Generic
Hexagon	[Hexagon] Add support for run-time stack overflow checking	2016-03-24 20:20:07 +00:00
Inputs
Mips	CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.	2016-03-24 15:38:38 +00:00
MIR	[MIR] Add a test case for the diagnostic of a wrongly typed generic instruction	2016-03-15 18:31:29 +00:00
MSP430
NVPTX	[NVPTX] Adds a new address space inference pass.	2016-03-20 20:59:20 +00:00
PowerPC	Finish the incomplete 'd' inline asm constraint support for PPC by	2016-03-24 21:04:52 +00:00
SPARC
SystemZ	[SystemZ] Avoid LER on z13 due to partial register dependencies	2016-03-14 13:50:03 +00:00
Thumb
Thumb2	ARM: Introduce conservative load/store optimization mode	2016-03-02 19:20:00 +00:00
WebAssembly	[WebAssembly] Implement the rotate instructions.	2016-03-22 18:01:49 +00:00
WinEH	[WinEH] Make setjmp work correctly with EH	2016-02-29 19:16:03 +00:00
X86	[X86] Use "and $0" and "orl $-1" to store 0 and -1 when optimizing for minsize	2016-03-25 18:11:31 +00:00
XCore