Craig Topper 1f33f8f1b9 [X86] Handle alls version of vXi1 insert_vector_elt with a constant index without falling back to shuffles. ...

We previously only supported inserting to the LSB or MSB where it was easy to zero to perform an OR to insert.

This change effectively extracts the old value and the new value, xors them together and then xors that single bit with the correct location in the original vector. This will cancel out the old value in the first xor leaving the new value in the position.

The way I've implemented this uses 3 shifts and two xors and uses an additional register. We can avoid the additional register at the cost of another shift.

llvm-svn: 320120

2017-12-08 00:16:09 +00:00

..

AArch64

[MachineOutliner] Fix offset overflow check

2017-12-07 21:51:43 +00:00

AMDGPU

[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output."

2017-12-07 21:14:41 +00:00

ARC

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ARM

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AVR

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

BPF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Generic

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Hexagon

[Hexagon] Generate HVX code for basic arithmetic operations

2017-12-07 17:37:28 +00:00

Inputs

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Lanai

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

Mips

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

MIR

Skip DBG instr in OptimizePHIs when looking for dead PHI cycles

2017-12-07 07:01:21 +00:00

MSP430

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Nios2

[Nios2] final infrastructure to provide compilation of a return from a function

2017-12-07 12:35:02 +00:00

NVPTX

[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.

2017-12-06 17:50:05 +00:00

PowerPC

Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions."

2017-12-07 22:26:19 +00:00

RISCV

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SPARC

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SystemZ

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

Thumb

[CodeGen] Always use printReg to print registers in both MIR and debug

2017-11-30 16:12:24 +00:00

Thumb2

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

WebAssembly

[WebAssemby] Support main functions with alternate signatures.

2017-12-07 13:49:27 +00:00

WinEH

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X86

[X86] Handle alls version of vXi1 insert_vector_elt with a constant index without falling back to shuffles.

2017-12-08 00:16:09 +00:00

XCore

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