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39a050b107
Previously, the code that implemented the GNU assembler aliases for the LDRD and STRD instructions (where the second register is omitted) assumed that the input was a valid instruction. This caused assertion failures for every example in ldrd-strd-gnu-bad-inst.s. This improves this code so that it bails out if the instruction is not in the expected format, the check bails out, and the asm parser is run on the unmodified instruction. It also relaxes the alias on thumb targets, so that unaligned pairs of registers can be used. The restriction that Rt must be even-numbered only applies to the ARM versions of these instructions. Differential revision: https://reviews.llvm.org/D36732 llvm-svn: 315305
36 lines
1.4 KiB
ArmAsm
36 lines
1.4 KiB
ArmAsm
@ PR18921
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@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
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.text
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.thumb
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@ CHECK: .code 16
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@ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
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@ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
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@ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
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ldrd r0, [r10, #512]!
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ldrd r0, [r10], #512
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ldrd r0, [r10, #512]
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@ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01]
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@ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01]
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@ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01]
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strd r0, [r10, #512]!
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strd r0, [r10], #512
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strd r0, [r10, #512]
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@ Rt is allowed to be odd for Thumb (but not ARM)
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@ CHECK: ldrd r1, r2, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x12]
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@ CHECK: ldrd r1, r2, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x12]
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@ CHECK: ldrd r1, r2, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x12]
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ldrd r1, [r10, #512]!
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ldrd r1, [r10], #512
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ldrd r1, [r10, #512]
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@ CHECK: strd r1, r2, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x12]
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@ CHECK: strd r1, r2, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x12]
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@ CHECK: strd r1, r2, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x12]
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strd r1, [r10, #512]!
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strd r1, [r10], #512
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strd r1, [r10, #512]
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