Tom Stellard 271c0a936e R600/SI: Make SIInstrInfo::isOperandLegal() more strict ... A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368		2014-11-19 16:58:49 +00:00
..
AArch64	[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.	2014-11-19 06:39:53 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.	2014-11-19 13:23:58 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PowerPC] Add VSX builtins for vec_div	2014-11-14 12:10:40 +00:00
R600	R600/SI: Make SIInstrInfo::isOperandLegal() more strict	2014-11-19 16:58:49 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2	2014-11-19 10:06:49 +00:00
XCore