Liu, Chen3 d3c2277000 Enable STRICT_FP_TO_SINT/UINT on X86 backend ... This patch is mainly for custom lowering the vector operation. Differential Revision: https://reviews.llvm.org/D71592		2019-12-19 14:49:13 +08:00
..
AArch64	Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat vector variant"	2019-12-18 14:14:10 -05:00
AMDGPU	[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr	2019-12-17 18:54:27 +00:00
ARC
ARM	Reapply: [DebugInfo] Correctly handle salvaged casts and split fragments at ISel	2019-12-18 16:26:42 +00:00
AVR
BPF	[BPF] put not-section-attribute externs into BTF ".extern" data section	2019-12-10 11:45:17 -08:00
Generic
Hexagon	[ModuloSchedule] Fix a bug in experimental expander	2019-11-23 16:01:47 -08:00
Inputs
Lanai
Mips	[Mips] Add support for min/max/umin/umax atomics	2019-12-12 11:32:37 +01:00
MIR	[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.	2019-12-16 18:25:04 -05:00
MSP430
NVPTX
PowerPC	[PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep pass	2019-12-18 21:06:57 -05:00
RISCV	[RISCV] Add subtargets initialized with target feature	2019-12-17 09:34:01 -08:00
SPARC	Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that	2019-12-03 11:21:52 +01:00
SystemZ	[FPEnv] Strict versions of llvm.minimum/llvm.maximum	2019-12-18 21:35:28 +01:00
Thumb	Revert "ARM-Darwin: keep the frame register reserved even if not updated."	2019-12-06 10:59:26 -08:00
Thumb2	[ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed numbers.	2019-12-13 17:29:59 +00:00
WebAssembly	[WebAssembly] Add avgr_u intrinsics and require nuw in patterns	2019-12-18 15:31:38 -08:00
WinCFGuard
WinEH
X86	Enable STRICT_FP_TO_SINT/UINT on X86 backend	2019-12-19 14:49:13 +08:00
XCore