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5dfc642fbd
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
119 lines
3.9 KiB
LLVM
119 lines
3.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}s_addk_i32_k0:
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; SI: s_load_dword [[VAL:s[0-9]+]]
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; SI: s_addk_i32 [[VAL]], 0x41
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[VRESULT]]
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_i32_k0(i32 addrspace(1)* %out, i32 %b) {
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%add = add i32 %b, 65
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store i32 %add, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This should be folded with any number of uses.
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; SI-LABEL: {{^}}s_addk_i32_k0_x2:
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; SI: s_movk_i32 [[K:s[0-9]+]], 0x41
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; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]]
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; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]]
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_i32_k0_x2(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %a, i32 %b) {
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%add0 = add i32 %a, 65
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%add1 = add i32 %b, 65
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store i32 %add0, i32 addrspace(1)* %out0
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store i32 %add1, i32 addrspace(1)* %out1
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ret void
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}
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; SI-LABEL: {{^}}s_addk_i32_k1:
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; SI: s_addk_i32 {{s[0-9]+}}, 0x7fff{{$}}
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_i32_k1(i32 addrspace(1)* %out, i32 %b) {
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%add = add i32 %b, 32767 ; (1 << 15) - 1
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store i32 %add, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_addk_i32_k2:
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; SI: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, 17
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_i32_k2(i32 addrspace(1)* %out, i32 %b) {
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%add = add i32 %b, -17
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store i32 %add, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_addk_i32_k3:
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; SI: s_addk_i32 {{s[0-9]+}}, 0xffbf{{$}}
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_i32_k3(i32 addrspace(1)* %out, i32 %b) {
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%add = add i32 %b, -65
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store i32 %add, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_addk_v2i32_k0:
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_v2i32_k0(<2 x i32> addrspace(1)* %out, <2 x i32> %b) {
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%add = add <2 x i32> %b, <i32 65, i32 66>
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store <2 x i32> %add, <2 x i32> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_addk_v4i32_k0:
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x43
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x44
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_v4i32_k0(<4 x i32> addrspace(1)* %out, <4 x i32> %b) {
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%add = add <4 x i32> %b, <i32 65, i32 66, i32 67, i32 68>
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store <4 x i32> %add, <4 x i32> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_addk_v8i32_k0:
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x43
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x44
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x45
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x46
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x47
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; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x48
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; SI: s_endpgm
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define amdgpu_kernel void @s_addk_v8i32_k0(<8 x i32> addrspace(1)* %out, <8 x i32> %b) {
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%add = add <8 x i32> %b, <i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72>
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store <8 x i32> %add, <8 x i32> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}no_s_addk_i32_k0:
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; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}}
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; SI: s_endpgm
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define amdgpu_kernel void @no_s_addk_i32_k0(i32 addrspace(1)* %out, i32 %b) {
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%add = add i32 %b, 32768 ; 1 << 15
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store i32 %add, i32 addrspace(1)* %out
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ret void
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}
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@lds = addrspace(3) global [512 x i32] undef, align 4
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; SI-LABEL: {{^}}commute_s_addk_i32:
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; SI: s_addk_i32 s{{[0-9]+}}, 0x800{{$}}
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define amdgpu_kernel void @commute_s_addk_i32(i32 addrspace(1)* %out, i32 %b) #0 {
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%size = call i32 @llvm.amdgcn.groupstaticsize()
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%add = add i32 %size, %b
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call void asm sideeffect "; foo $0, $1", "v,s"([512 x i32] addrspace(3)* @lds, i32 %add)
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ret void
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}
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declare i32 @llvm.amdgcn.groupstaticsize() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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