..
GlobalISel
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
32-bit-local-address-space.ll
add_i64.ll
add_i128.ll
add-debug.ll
add.i16.ll
add.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
add.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
addrspacecast.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
adjust-writemask-invalid-copy.ll
AMDGPU: image_getlod and image_getresinfo do not read memory
2017-12-08 20:00:57 +00:00
alignbit-pat.ll
alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
always-uniform.ll
amdgcn.bitcast.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
amdgcn.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-alias-analysis.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-inline.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
amdgpu-shader-calling-convention.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
amdgpu.private-memory.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdpal-cs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-es.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-gs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-hs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-ls.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-ps.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal-psenable.ll
[AMDGPU] For amdpal, widen interpolation mode workaround
2017-10-12 16:16:41 +00:00
amdpal-vs.ll
AMDGPU/NFC: Minor clean ups in PAL metadata
2017-10-11 22:41:09 +00:00
amdpal.ll
[AMDGPU] do not generate .AMDGPU.config for amdpal os type
2018-02-06 13:39:38 +00:00
and-gcn.ll
and.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
annotate-kernel-features-hsa-call.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features-hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
AMDGPU: Set v2i32 any_extend to expand
2017-10-05 17:38:30 +00:00
array-ptr-calc-i32.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
array-ptr-calc-i64.ll
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
2017-11-13 22:55:05 +00:00
ashr.v2i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
atomic_cmp_swap_local.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
atomic_load_add.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
atomic_load_sub.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistency
2017-10-18 17:31:09 +00:00
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
bfe-patterns.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
bfi_int.ll
AMDGPU: Select BFI patterns with 64-bit ints
2018-02-07 00:21:34 +00:00
bfm.ll
big_alu.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
br_cc.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
branch-relaxation.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
branch-uniformity.ll
break-smem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
break-vmem-soft-clauses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
bswap.ll
DAG: Fix not truncating when promoting bswap/bitreverse
2018-01-31 23:54:16 +00:00
bug-vopc-commute.ll
build_vector.ll
byval-frame-setup.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
call_fs.ll
call-argument-types.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
call-encoding.ll
call-graph-register-usage.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
call-preserved-registers.ll
AMDGPU: Enable IPRA
2017-11-28 23:40:12 +00:00
call-return-types.ll
CodeGen: Fix TargetLowering::LowerCallTo for sret value type
2017-11-14 18:46:52 +00:00
callee-frame-setup.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
callee-special-input-sgprs.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
callee-special-input-vgprs.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
calling-conventions.ll
captured-frame-index.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
cayman-loop-bug.ll
cf_end.ll
cf-loop-on-constant.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-addressing-modes.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
cgp-bitfield-extract.ll
clamp-modifier.ll
clamp-omod-special-case.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
clamp.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
cluster-flat-loads-postra.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cluster-flat-loads.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
cndmask-no-def-vcc.ll
coalescer_distribute.ll
coalescer_remat.ll
coalescer-subrange-crash.ll
coalescer-subreg-join.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
combine_vloads.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
commute_modifiers.ll
commute-compares.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
commute-shifts.ll
complex-folding.ll
concat_vectors.ll
[DAGCombiner] Bail out if vector size is not a multiple
2018-01-24 09:53:47 +00:00
constant-address-space-32bit.ll
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
constant-fold-imm-immreg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
control-flow-optnone.ll
AMDGPU: Fix missing skipFunction calls
2017-10-10 20:48:36 +00:00
convergent-inlineasm.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
copy-illegal-type.ll
copy-to-reg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
ctlz_zero_undef.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctlz.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctpop64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
ctpop.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
cttz_zero_undef.ll
[DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero
2018-02-06 23:54:37 +00:00
cube.ll
cvt_f32_ubyte.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dagcomb-shuffle-vecextend-non2.ll
[DAGCombine] Fix for shuffle to vector extend for non power 2 vectors
2017-10-10 12:45:45 +00:00
dagcombine-reassociate-bug.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
debug-value2.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
debug-value.ll
Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
2017-12-15 03:56:57 +00:00
debug.ll
debugger-emit-prologue.ll
Fix APInt bit size in processDbgDeclares
2017-11-16 02:54:49 +00:00
debugger-insert-nops.ll
Fix APInt bit size in processDbgDeclares
2017-11-16 02:54:49 +00:00
debugger-reserve-regs.ll
Fix APInt bit size in processDbgDeclares
2017-11-16 02:54:49 +00:00
default-fp-mode.ll
detect-dead-lanes.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
disconnected-predset-break-bug.ll
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds_read2st64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds_write2.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds_write2st64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
ds-combine-large-stride.ll
[AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64
2018-01-22 21:46:43 +00:00
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
dynamic_stackalloc.ll
Fix pointer EVT in SelectionDAGBuilder::visitAlloca
2017-11-16 12:22:19 +00:00
early-if-convert-cost.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-if-convert.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
early-inline-alias.ll
early-inline.ll
[PassManager] Run global optimizations after the inliner.
2017-10-05 18:06:37 +00:00
elf-header.ll
elf-notes.ll
AMDGPU: Temporary disable pal metadata check line in llvm-readobj test
2017-10-14 23:42:11 +00:00
elf.ll
elf.r600.ll
else.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
enqueue-kernel.ll
Make internal/private GVs implicitly dso_local.
2018-01-11 22:15:05 +00:00
env-amdgiz.ll
env-amdgizcl.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
[CodeGen] Don't print register classes in -debug output
2018-01-09 15:39:44 +00:00
extload-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
extload.ll
extract_vector_elt-f16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
extract_vector_elt-f64.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
extract_vector_elt-i8.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
extract_vector_elt-i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
extract_vector_elt-i64.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fabs.f64.ll
fabs.ll
AMDGPU: Implement hasBitPreservingFPLogic
2017-10-13 21:10:22 +00:00
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
fcanonicalize-elimination.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fcanonicalize.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fcanonicalize.ll
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fcopysign.f32.ll
fcopysign.f64.ll
fdiv.f16.ll
fdiv.f64.ll
fdiv.ll
fence-amdgiz.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fence-barrier.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
[MachineCopyPropagation] Extend pass to do COPY source forwarding
2018-02-01 18:54:01 +00:00
fix-wwm-liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat_atomics_i64.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat_atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-address-space.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-for-global-subtarget-feature.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
flat-load-clustering.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
flat-scratch-reg.ll
floor.ll
fma-combine.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
fma.f64.ll
fma.ll
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
fmad.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f64.ll
fmax_legacy.ll
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fmin3.ll
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f64.ll
fmin_legacy.ll
fmin.ll
fminnum.f64.ll
fminnum.ll
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmuladd.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
fmuladd.f32.ll
DAG: Fold fma (fneg x), K, y -> fma x, -K, y
2017-10-27 09:06:07 +00:00
fmuladd.f64.ll
fmuladd.v2f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fnearbyint.ll
fneg-combines.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
fneg-fabs.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fneg-fabs.f64.ll
fneg-fabs.ll
fneg.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fneg.f64.ll
fneg.ll
AMDGPU: Implement hasBitPreservingFPLogic
2017-10-13 21:10:22 +00:00
fold-cndmask.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-fmul-to-neg-abs.ll
fold-imm-f16-f32.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-immediate-output-mods.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-implicit-operand.mir
AMDGPU: Don't crash when trying to fold implicit operands
2018-02-08 01:12:46 +00:00
fold-multiple.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fold-operands-order.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fp-classify.ll
fpext-free.ll
AMDGPU: Look for src mods before fp_extend
2017-10-13 20:45:49 +00:00
fpext.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-amdgiz.ll
frame-index-elimination.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
function-returns.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
gep-address-space.ll
global_atomics_i64.ll
global_atomics.ll
global_smrd_cfg.ll
global_smrd.ll
global-constant.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
global-directive.ll
global-extload-i16.ll
global-smrd-unknown.ll
global-variable-relocs.ll
gv-const-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
gv-offset-folding.ll
half.ll
hazard-inlineasm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-func.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg.ll
AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available
2017-12-08 19:22:12 +00:00
hsa-metadata-enqueu-kernel.ll
AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available
2017-12-08 19:22:12 +00:00
hsa-metadata-from-llvm-ir-full.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
hsa-metadata-images.ll
AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available
2017-12-08 19:22:12 +00:00
hsa-metadata-invalid-ocl-version-1.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-2.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-invalid-ocl-version-3.ll
llvm-readobj: Print AMDGPU note contents
2017-10-14 18:21:42 +00:00
hsa-metadata-kernel-code-props.ll
AMDGPU: Add num spilled s/vgprs to metadata
2017-11-28 17:51:08 +00:00
hsa-metadata-kernel-debug-props.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
hsa-note-no-func.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
hsa.ll
huge-private-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
i1-copy-implicit-def.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
image-schedule.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
imm16.ll
imm.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
immv216.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
indirect-addressing-si-noopt.ll
AMDGPU Tests: Change a case to be run with -O0
2017-12-06 17:40:09 +00:00
indirect-addressing-si.ll
2nd attempt at "fixing" amdgpu tests after r321575
2017-12-31 03:34:36 +00:00
indirect-private-64.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
InlineAsmCrash.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
input-mods.ll
insert_subreg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
insert_vector_elt.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
insert_vector_elt.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
insert-skips-kill-uncond.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
insert-waits-callee.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
insert-waits-exp.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
inserted-wait-states.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
internalize.ll
invalid-addrspacecast.ll
invalid-alloca.ll
LLParser: add an argument for overriding data layout and do not check alloca addr space
2018-01-30 22:32:39 +00:00
invariant-load-no-alias-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
ipra.ll
AMDGPU: Enable IPRA
2017-11-28 23:40:12 +00:00
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
kernel-args.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
knownbits-recursion.ll
large-alloca-compute.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-alloca-graphics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lds_atomic_f32.ll
[AMDGPU] fix LDS f32 intrinsics
2018-01-26 11:09:38 +00:00
lds-alignment.ll
[NFC] fix trivial typos in comments and documents
2018-01-29 05:17:03 +00:00
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
2017-11-30 12:12:19 +00:00
lds-size.ll
lds-zero-initializer.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
lit.local.cfg
literals.ll
liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
llvm.amdgcn.buffer.atomic.ll
AMDGPU: Lower buffer store and atomic intrinsics manually
2017-11-09 01:52:48 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.buffer.load.format.ll
AMDGPU: Split MUBUF offset into aligned components
2017-10-10 12:22:23 +00:00
llvm.amdgcn.buffer.load.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.store.format.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.buffer.store.format.ll
AMDGPU: Lower buffer store and atomic intrinsics manually
2017-11-09 01:52:48 +00:00
llvm.amdgcn.buffer.store.ll
AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4
2017-11-09 01:52:55 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
llvm.amdgcn.cvt.pkrtz.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.div.fixup.f16.ll
AMDGPU: Fix breaking SMEM clauses
2017-11-17 04:18:24 +00:00
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.exp.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fmed3.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.atomic.ll
AMDGPU: Lower buffer store and atomic intrinsics manually
2017-11-09 01:52:48 +00:00
llvm.amdgcn.image.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.image.gather4.d16.ll
AMDGPU/SI: Add d16 support for image intrinsics.
2018-01-18 22:08:53 +00:00
llvm.amdgcn.image.gather4.ll
llvm.amdgcn.image.getlod.ll
AMDGPU: image_getlod and image_getresinfo do not read memory
2017-12-08 20:00:57 +00:00
llvm.amdgcn.image.ll
[AMDGPU] stop image_store being moved illegally
2018-01-12 22:57:24 +00:00
llvm.amdgcn.image.sample.d16.ll
AMDGPU/SI: Add d16 support for image intrinsics.
2018-01-18 22:08:53 +00:00
llvm.amdgcn.image.sample.ll
llvm.amdgcn.image.sample.o.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
llvm.amdgcn.interp.ll
llvm.amdgcn.kernarg.segment.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.kill.ll
AMDGPU: Allow a SGPR for the conditional KILL operand
2018-01-29 23:19:10 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
2017-11-13 22:55:05 +00:00
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.dcache.inv.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
2017-12-29 17:18:18 +00:00
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.tbuffer.load.d16.ll
AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
2018-02-01 18:41:33 +00:00
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
[AMDGPU] Remove non-temporal flag from argument loads
2018-02-14 18:05:14 +00:00
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
2017-10-24 10:26:59 +00:00
llvm.AMDGPU.kill.ll
llvm.amdgpu.kilp.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll
llvm.cos.ll
llvm.dbg.value.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
llvm.fmuladd.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log10.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log.f16.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.log.ll
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
2017-11-27 13:26:38 +00:00
llvm.maxnum.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
llvm.memcpy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.minnum.f16.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.SI.load.dword.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.SI.tbuffer.store.ll
llvm.sin.f16.ll
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
load-constant-f64.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i1.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i8.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i32.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-constant-i64.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
[AMDGPU] Fix pointer info for pseudo source for r600
2017-11-10 01:53:24 +00:00
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-input-fold.ll
load-lo16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
load-local-f32.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-f64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i1.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i8.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i16.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i32.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-local-i64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
load-private-double16-amdgiz.ll
load-weird-sizes.ll
local-64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-atomics64.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-atomics.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
loop_break.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
loop-address.ll
loop-idiom.ll
lower-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
macro-fusion-cluster-vcc-uses.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mad24-get-global-id.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mad_64_32.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
mad_int24.ll
mad_uint24.ll
mad-combine.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
mad-mix-hi.ll
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
2017-11-17 15:15:40 +00:00
mad-mix-lo.ll
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
2017-11-17 15:15:40 +00:00
mad-mix.ll
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
2017-11-17 15:15:40 +00:00
madak.ll
madmk.ll
max3.ll
max-literals.ll
max.i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
max.ll
mem-builtins.ll
memory-legalizer-atomic-cmpxchg.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-fence.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-atomic-insert-end.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
memory-legalizer-atomic-rmw.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
memory-legalizer-load.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
memory-legalizer-store-infinite-loop.ll
[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.
2017-12-19 19:26:23 +00:00
memory-legalizer-store.ll
[AMDGPU] Cleanup in memory legalizer tests. NFC.
2018-02-13 20:03:32 +00:00
merge-load-store-vreg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-load-store.mir
AMDGPU: Fix incorrect reordering when inline asm defines LDS address
2018-02-08 01:56:14 +00:00
merge-m0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4
2017-11-09 01:52:55 +00:00
mesa_regression.ll
min3.ll
min.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
misched-killflags.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
missing-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
movreld-bug.ll
movrels-bug.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
mubuf-offset-private.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
mubuf-shader-vgpr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mubuf.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
multi-divergent-exit-region.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
multilevel-break.ll
[MachineCopyPropagation] Extend pass to do COPY source forwarding
2018-02-01 18:54:01 +00:00
nested-calls.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
nested-loop-conditions.ll
Revert r321751, "StructurizeCFG: Fix broken backedge detection"
2018-01-24 18:02:05 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
no-shrink-extloads.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
nop-data.ll
not-scalarize-volatile-load.ll
nullptr.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll
opt-sgpr-to-vgpr-copy.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
optimize-if-exec-masking.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
or.ll
over-max-lds-size.ll
pack.v2f16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
pack.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
packed-op-sel.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
packetizer.ll
parallelandifcollapse.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partially-dead-super-register-immediate.ll
predicate-dp4.ll
predicates.ll
private-access-no-objects.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-element-size.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-r600.ll
[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
2017-11-06 14:32:33 +00:00
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-calling-conv.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-globals.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-invariant-markers.ll
Let llvm.invariant.group.barrier accepts pointer to any address space
2017-11-16 16:32:16 +00:00
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
promote-alloca-no-opts.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-padding-size-estimate.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-stored-pointer-value.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
promote-alloca-unhandled-intrinsic.ll
promote-alloca-volatile.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll
[AMDGPU] Update test r600.amdgpu-alias-analysis.ll
2017-11-20 16:53:13 +00:00
r600.bitcast.ll
r600.global_atomics.ll
r600.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.work-item-intrinsics.ll
[SelectionDAG] Provide adequate register class for RegisterSDNode
2018-02-09 13:55:25 +00:00
r600cfg.ll
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
readlane_exec0.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
README
reduce-load-width-alignment.ll
reduce-saveexec.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reduce-store-width-alignment.ll
reg-coalescer-sched-crash.ll
regcoal-subrange-join.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regcoalesce-dbg.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
regcoalesce-prune.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
rename-independent-subregs.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
reorder-stores.ll
ret_jump.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ret.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotl.ll
rotr.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
saddo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
salu-to-valu.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sampler-resource-id.ll
scalar_to_vector.ll
scalar-branch-missing-and-exec.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
scalar-store-cache-flush.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sched-crash-dbg-value.mir
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
schedule-regpressure-limit.ll
schedule-regpressure.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
scratch-buffer.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
scratch-simple.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
sdiv.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sdivrem24.ll
sdivrem64.ll
[AMDGPU] New 64 bit div/rem expansion
2017-10-06 17:24:45 +00:00
sdwa-gfx9.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole-instr.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-peephole.ll
AMDGPU: Minor cleanups
2018-02-08 22:46:38 +00:00
sdwa-preserve.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-scalar-ops.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdwa-vop2-64bit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
select-opt.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
select-vectors.ll
select.f16.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
selected-stack-object.ll
sendmsg-m0-hazard.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sgpr-control-flow.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
sgpr-copy-duplicate-operand.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
sgpr-copy.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sgprcopies.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shl_add_constant.ll
shl_add_ptr.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
shl-add-to-add-shl.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
shl.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
shl.v2i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
shrink-add-sub-constant.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
shrink-carry.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
shrink-vop3-carry-out.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
si-annotate-cfg-loop-assert.ll
si-fix-sgpr-copies.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-instr-info-correct-implicit-operands.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
si-lod-bias.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
si-scheduler.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-sgpr-spill.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
si-vector-hang.ll
sibling-call.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sign_extend.ll
simplify-libcalls.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
simplifydemandedbits-recursion.ll
Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats).
2017-10-16 23:38:53 +00:00
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
skip-if-dead.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
smed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
sminmax.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sminmax.v2i16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
smrd-vccz-bug.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
smrd.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
sopk-compares.ll
spill-alloc-sgpr-init-bug.ll
spill-cfg-position.ll
spill-empty-live-interval.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
spill-m0.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-wide-sgpr.ll
split-scalar-i64-add.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
split-smrd.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sra.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
srem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
srl.ll
ssubo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
stack-size-overflow.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store_typed.ll
store-barrier.ll
store-global.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-hi16.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store-local.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
store-private.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
store-v3i64.ll
store-vector-ptrs.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store-weird-sizes.ll
AMDGPU: Select DS insts without m0 initialization
2017-11-29 00:55:57 +00:00
stress-calls.ll
structurize1.ll
structurize.ll
sub.i16.ll
AMDGPU: Replace i64 add/sub lowering
2017-11-15 21:51:43 +00:00
sub.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
sub.v2i16.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
subreg_interference.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
subreg-eliminate-dead.ll
subreg-intervals.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
swizzle-export.ll
syncscopes.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
tail-call-cgp.ll
target-cpu.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
2017-11-10 02:03:28 +00:00
trunc.ll
tti-unroll-prefs.ll
twoaddr-mad.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
uaddo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
udiv.ll
udivrem24.ll
udivrem64.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
udivrem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
uint_to_fp.f64.ll
uint_to_fp.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
uint_to_fp.ll
uitofp.f16.ll
umed3.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
unaligned-load-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
undefined-physreg-sgpr-spill.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
undefined-subreg-liverange.ll
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
[AMDGPU] Fixed incorrect uniform branch condition
2018-01-09 21:34:43 +00:00
uniform-crash.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll
[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHI
2017-12-01 11:56:34 +00:00
uniform-PHI.ll
[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHI
2017-12-01 11:56:34 +00:00
unify-metadata.ll
unigine-liveness-crash.ll
unknown-processor.ll
[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
2017-11-06 14:32:33 +00:00
unpack-half.ll
[SelectionDAG] Fixed f16-from-vector promotion problem
2018-01-09 21:36:25 +00:00
unroll.ll
unsupported-calls.ll
[AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit
2017-11-06 13:01:33 +00:00
unsupported-cc.ll
urem.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
use-sgpr-multiple-times.ll
AMDGPU: Fix breaking SMEM clauses
2017-11-17 04:18:24 +00:00
usubo.ll
AMDGPU: Use gfx9 carry-less add/sub instructions
2017-11-30 22:51:26 +00:00
v1i64-kernel-arg.ll
v_cndmask.ll
AMDGPU: Fix -enable-var-scope violations
2017-11-12 23:53:44 +00:00
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
valu-i1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vccz-corrupt-bug-workaround.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vector-alloca.ll
[AMDGPU] Fix pointer info for pseudo source for r600
2017-11-10 01:53:24 +00:00
vector-extract-insert.ll
vectorize-global-local.ll
vertex-fetch-encoding.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vgpr-spill-emergency-stack-slot-compute.ll
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
2017-12-02 22:13:22 +00:00
vgpr-spill-emergency-stack-slot.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vi-removed-intrinsics.ll
vop-shrink-frame-index.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
vop-shrink-non-ssa.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vop-shrink.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
waitcnt-flat.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
waitcnt-looptest.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
waitcnt-no-redundant.mir
[AMDGPU] Suppress redundant waitcnt instrs.
2018-02-07 02:21:21 +00:00
waitcnt-permute.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
waitcnt.mir
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
widen_extending_scalar_loads.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
widen-vselect-and-mask.ll
DAG: Fix creating select with wrong condition type
2017-10-25 07:14:07 +00:00
wqm.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
wqm.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
xfail.r600.bitcast.ll
xnor.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll
AMDGPU: Fix default range in non-kernel functions
2017-10-23 17:09:35 +00:00
