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https://github.com/RPCS3/llvm-mirror.git
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5dfc642fbd
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. llvm-svn: 310258
259 lines
9.4 KiB
LLVM
259 lines
9.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.
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; GCN-LABEL: {{^}}multi_use_fneg_src:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[A]], [[B]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]]
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; GCN: buffer_store_dword [[MUL]]
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define amdgpu_kernel void @multi_use_fneg_src() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %mul, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_foldable_use_fneg_src:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[A]], [[B]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[A]]
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; GCN: v_mul_f32_e64 [[USE1:v[0-9]+]], [[MUL]], -[[MUL]]
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define amdgpu_kernel void @multi_foldable_use_fneg_src() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%use1 = fmul float %mul, %neg.mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %use1, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_use_fneg:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[A]], -[[B]]
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; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 4.0, [[MUL]]
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; GCN-NOT: xor
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; GCN: buffer_store_dword [[MUL]]
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define amdgpu_kernel void @multi_use_fneg() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %neg.mul, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_foldable_use_fneg:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL0:v[0-9]+]], [[A]], [[B]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL0]]
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; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MUL0]], [[MUL0]]
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; GCN: buffer_store_dword [[MUL1]]
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define amdgpu_kernel void @multi_foldable_use_fneg() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%z = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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%use1 = fmul float %neg.mul, %mul
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %use1, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32:
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_oeq_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp oeq float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32:
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; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ogt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ogt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32:
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; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_oge_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp oge float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32:
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; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_olt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp olt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32:
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; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ole_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ole float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32:
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; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_one_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp one float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32:
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; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ueq_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ueq float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32:
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; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ugt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ugt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32:
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; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_uge_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp uge float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32:
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; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ult_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ult float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32:
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; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_ule_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ule float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32:
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; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define amdgpu_kernel void @test_setcc_fneg_une_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp une float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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