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88ae65cfbd
* Add lowering for SETCCE i32. * Add test to check lowering of i64 compares uses SETCCE expansion (outside of EQ and NE). * Fix select.ll test and immediate form selection for RI operations. llvm-svn: 266802
42 lines
1.1 KiB
LLVM
42 lines
1.1 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; Test that Lanai select instruction is selected from LLVM select instruction.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: select_i32_bool:
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; CHECK: sub.f %r6, 0x0, %r0
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; CHECK: sel.ne %r7, %r18, %rv
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define i32 @select_i32_bool(i1 zeroext inreg %a, i32 inreg %b, i32 inreg %c) {
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%cond = select i1 %a, i32 %b, i32 %c
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ret i32 %cond
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}
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; CHECK-LABEL: select_i32_eq:
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; CHECK: sub.f %r6, 0x0, %r0
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; CHECK: sel.eq %r7, %r18, %rv
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define i32 @select_i32_eq(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
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%cmp = icmp eq i32 %a, 0
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%cond = select i1 %cmp, i32 %b, i32 %c
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ret i32 %cond
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}
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; CHECK-LABEL: select_i32_ne:
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; CHECK: sub.f %r6, 0x0, %r0
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; CHECK: sel.ne %r7, %r18, %rv
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define i32 @select_i32_ne(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
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%cmp = icmp ne i32 %a, 0
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%cond = select i1 %cmp, i32 %b, i32 %c
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ret i32 %cond
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}
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; CHECK-LABEL: select_i32_lt:
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; CHECK: sub.f %r6, %r7, %r0
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; CHECK: sel.lt %r6, %r7, %rv
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define i32 @select_i32_lt(i32 inreg %x, i32 inreg %y) #0 {
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%1 = icmp slt i32 %x, %y
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%2 = select i1 %1, i32 %x, i32 %y
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ret i32 %2
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}
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