Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil. ... Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922		2018-01-31 22:04:26 +00:00
..
codemodel.ll	[lanai] Simplify small section check in LowerGlobalAddress and treat ldata sections specially.	2016-12-15 16:56:16 +00:00
comparisons_i32.ll
comparisons_i64.ll	[lanai] Add lowering for SETCCE i32.	2016-04-19 19:15:25 +00:00
constant_multiply.ll	[lanai] Manually match 0/-1 with R0/R1.	2016-11-29 23:01:09 +00:00
delay_filler.ll
i32.ll
lanai-misched-trivial-disjoint.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
lit.local.cfg
lshift64.ll	[lanai] Custom lowering of SHL_PARTS	2016-12-02 22:01:28 +00:00
masking_setccs.ll	[lanai] Add computeKnownBitsForTargetNode for Lanai.	2017-05-09 18:35:26 +00:00
mem_alu_combiner.ll	[lanai] Change reloc to use PIC_ by default and cleanup.	2016-05-20 21:41:53 +00:00
multiply.ll
peephole-compare.mir	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
rshift64.ll	[lanai] Add custom lowering for SRL_PARTS i32.	2016-04-14 17:59:22 +00:00
select.ll	[lanai] Add lowering for SETCCE i32.	2016-04-19 19:15:25 +00:00
set_and_hi.ll
shift.ll
stack-frame.ll
sub-cmp-peephole.ll	[lanai] Use peephole optimizer to generate more conditional ALU operations.	2016-07-07 23:36:04 +00:00
subword.ll	[lanai] Add subword scheduling itineraries.	2016-04-20 18:28:55 +00:00