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This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
39 lines
1.5 KiB
Plaintext
39 lines
1.5 KiB
Plaintext
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
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# A8.8.116 MVN (register)
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# MVN(S)<c> <Rd>, <Rm>{, <shift>}
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#
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
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# -------------------------------------------------------------------------------------------------
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# MVN r2, r3 ; with bit 16 == 1 => Unpredictable
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# CHECK: potentially undefined
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# CHECK: 0x03 0x20 0xe1 0xe1
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0x03 0x20 0xe1 0xe1
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# A8.8.117 MVN (register-shifted register)
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# MVN(S)<c> <Rd>, <Rm>, <type> <Rs>
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#
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | Rs | 0|type | 1| Rm |
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# -------------------------------------------------------------------------------------------------
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# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
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# MVN r5, pc, lsl r7
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# CHECK: potentially undefined
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# CHECK: 0x1f 0x57 0xe0 0xe1
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0x1f 0x57 0xe0 0xe1
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# MVN pc, r6, lsl r7
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# CHECK: potentially undefined
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# CHECK: 0x16 0xf7 0xe0 0xe1
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0x16 0xf7 0xe0 0xe1
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# MVN r5, r6, lsl pc
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# CHECK: potentially undefined
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# CHECK: 0x16 0x5f 0xe0 0xe1
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0x16 0x5f 0xe0 0xe1
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