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729 lines
18 KiB
TableGen
729 lines
18 KiB
TableGen
//=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon duplex instructions.
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//
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//===----------------------------------------------------------------------===//
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// SA1_combine1i: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combine1i: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins u2Imm:$u2),
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"$Rdd = combine(#1, #$u2)"> {
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bits<3> Rdd;
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bits<2> u2;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b0;
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let Inst{4-3} = 0b01;
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let Inst{2-0} = Rdd;
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let Inst{6-5} = u2;
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}
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// SL2_jumpr31_f: Indirect conditional jump if false.
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// SL2_jumpr31_f -> SL2_jumpr31_fnew
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let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
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def V4_SL2_jumpr31_f: SUBInst <
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(outs ),
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(ins ),
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"if (!p0) jumpr r31"> {
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let Inst{12-6} = 0b1111111;
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let Inst{2-0} = 0b101;
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}
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// SL2_deallocframe: Deallocate stack frame.
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let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
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def V4_SL2_deallocframe: SUBInst <
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(outs ),
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(ins ),
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"deallocframe"> {
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let Inst{12-6} = 0b1111100;
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let Inst{2} = 0b0;
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}
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// SL2_return_f: Deallocate stack frame and return.
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// SL2_return_f -> SL2_return_fnew
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let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
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def V4_SL2_return_f: SUBInst <
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(outs ),
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(ins ),
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"if (!p0) dealloc_return"> {
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let Inst{12-6} = 0b1111101;
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let Inst{2-0} = 0b101;
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}
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// SA1_combine3i: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combine3i: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins u2Imm:$u2),
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"$Rdd = combine(#3, #$u2)"> {
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bits<3> Rdd;
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bits<2> u2;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b0;
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let Inst{4-3} = 0b11;
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let Inst{2-0} = Rdd;
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let Inst{6-5} = u2;
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}
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// SS2_storebi0: Store byte.
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let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
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def V4_SS2_storebi0: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u4_0Imm:$u4_0),
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"memb($Rs + #$u4_0)=#0"> {
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bits<4> Rs;
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bits<4> u4_0;
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let Inst{12-8} = 0b10010;
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let Inst{7-4} = Rs;
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let Inst{3-0} = u4_0;
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}
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// SA1_clrtnew: Clear if true.
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let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_clrtnew: SUBInst <
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(outs IntRegs:$Rd),
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(ins ),
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"if (p0.new) $Rd = #0"> {
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bits<4> Rd;
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let Inst{12-9} = 0b1101;
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let Inst{6-4} = 0b100;
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let Inst{3-0} = Rd;
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}
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// SL2_loadruh_io: Load half.
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let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
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def V4_SL2_loadruh_io: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u3_1Imm:$u3_1),
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"$Rd = memuh($Rs + #$u3_1)"> {
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bits<4> Rd;
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bits<4> Rs;
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bits<4> u3_1;
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let Inst{12-11} = 0b01;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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let Inst{10-8} = u3_1{3-1};
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}
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// SL2_jumpr31_tnew: Indirect conditional jump if true.
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let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
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def V4_SL2_jumpr31_tnew: SUBInst <
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(outs ),
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(ins ),
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"if (p0.new) jumpr:nt r31"> {
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let Inst{12-6} = 0b1111111;
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let Inst{2-0} = 0b110;
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}
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// SA1_addi: Add.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in
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def V4_SA1_addi: SUBInst <
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(outs IntRegs:$Rx),
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(ins IntRegs:$_src_, s7Ext:$s7),
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"$Rx = add($_src_, #$s7)" ,
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[] ,
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"$_src_ = $Rx"> {
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bits<4> Rx;
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bits<7> s7;
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let Inst{12-11} = 0b00;
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let Inst{3-0} = Rx;
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let Inst{10-4} = s7;
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}
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// SL1_loadrub_io: Load byte.
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let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
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def V4_SL1_loadrub_io: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u4_0Imm:$u4_0),
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"$Rd = memub($Rs + #$u4_0)"> {
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bits<4> Rd;
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bits<4> Rs;
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bits<4> u4_0;
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let Inst{12} = 0b1;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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let Inst{11-8} = u4_0;
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}
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// SL1_loadri_io: Load word.
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let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
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def V4_SL1_loadri_io: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u4_2Imm:$u4_2),
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"$Rd = memw($Rs + #$u4_2)"> {
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bits<4> Rd;
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bits<4> Rs;
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bits<6> u4_2;
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let Inst{12} = 0b0;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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let Inst{11-8} = u4_2{5-2};
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}
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// SA1_cmpeqi: Compareimmed.
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let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_cmpeqi: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u2Imm:$u2),
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"p0 = cmp.eq($Rs, #$u2)"> {
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bits<4> Rs;
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bits<2> u2;
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let Inst{12-8} = 0b11001;
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let Inst{7-4} = Rs;
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let Inst{1-0} = u2;
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}
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// SA1_combinerz: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combinerz: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins IntRegs:$Rs),
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"$Rdd = combine($Rs, #0)"> {
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bits<3> Rdd;
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bits<4> Rs;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b1;
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let Inst{3} = 0b1;
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let Inst{2-0} = Rdd;
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let Inst{7-4} = Rs;
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}
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// SL2_return_t: Deallocate stack frame and return.
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// SL2_return_t -> SL2_return_tnew
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let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
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def V4_SL2_return_t: SUBInst <
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(outs ),
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(ins ),
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"if (p0) dealloc_return"> {
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let Inst{12-6} = 0b1111101;
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let Inst{2-0} = 0b100;
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}
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// SS2_allocframe: Allocate stack frame.
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let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
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def V4_SS2_allocframe: SUBInst <
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(outs ),
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(ins u5_3Imm:$u5_3),
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"allocframe(#$u5_3)"> {
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bits<8> u5_3;
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let Inst{12-9} = 0b1110;
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let Inst{8-4} = u5_3{7-3};
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}
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// SS2_storeh_io: Store half.
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let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in
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def V4_SS2_storeh_io: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt),
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"memh($Rs + #$u3_1) = $Rt"> {
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bits<4> Rs;
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bits<4> u3_1;
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bits<4> Rt;
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let Inst{12-11} = 0b00;
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let Inst{7-4} = Rs;
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let Inst{10-8} = u3_1{3-1};
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let Inst{3-0} = Rt;
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}
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// SS2_storewi0: Store word.
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let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
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def V4_SS2_storewi0: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u4_2Imm:$u4_2),
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"memw($Rs + #$u4_2)=#0"> {
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bits<4> Rs;
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bits<6> u4_2;
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let Inst{12-8} = 0b10000;
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let Inst{7-4} = Rs;
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let Inst{3-0} = u4_2{5-2};
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}
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// SS2_storewi1: Store word.
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let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
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def V4_SS2_storewi1: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u4_2Imm:$u4_2),
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"memw($Rs + #$u4_2)=#1"> {
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bits<4> Rs;
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bits<6> u4_2;
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let Inst{12-8} = 0b10001;
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let Inst{7-4} = Rs;
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let Inst{3-0} = u4_2{5-2};
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}
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// SL2_jumpr31: Indirect conditional jump if true.
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let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
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def V4_SL2_jumpr31: SUBInst <
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(outs ),
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(ins ),
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"jumpr r31"> {
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let Inst{12-6} = 0b1111111;
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let Inst{2} = 0b0;
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}
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// SA1_combinezr: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combinezr: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins IntRegs:$Rs),
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"$Rdd = combine(#0, $Rs)"> {
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bits<3> Rdd;
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bits<4> Rs;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b1;
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let Inst{3} = 0b0;
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let Inst{2-0} = Rdd;
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let Inst{7-4} = Rs;
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}
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// SL2_loadrh_io: Load half.
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let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
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def V4_SL2_loadrh_io: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u3_1Imm:$u3_1),
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"$Rd = memh($Rs + #$u3_1)"> {
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bits<4> Rd;
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bits<4> Rs;
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bits<4> u3_1;
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let Inst{12-11} = 0b00;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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let Inst{10-8} = u3_1{3-1};
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}
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// SA1_addrx: Add.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_addrx: SUBInst <
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(outs IntRegs:$Rx),
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(ins IntRegs:$_src_, IntRegs:$Rs),
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"$Rx = add($_src_, $Rs)" ,
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[] ,
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"$_src_ = $Rx"> {
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bits<4> Rx;
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bits<4> Rs;
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let Inst{12-8} = 0b11000;
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let Inst{3-0} = Rx;
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let Inst{7-4} = Rs;
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}
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// SA1_setin1: Set to -1.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_setin1: SUBInst <
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(outs IntRegs:$Rd),
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(ins ),
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"$Rd = #-1"> {
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bits<4> Rd;
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let Inst{12-9} = 0b1101;
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let Inst{6} = 0b0;
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let Inst{3-0} = Rd;
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}
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// SA1_sxth: Sxth.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_sxth: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs),
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"$Rd = sxth($Rs)"> {
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bits<4> Rd;
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bits<4> Rs;
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let Inst{12-8} = 0b10100;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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}
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// SA1_combine0i: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combine0i: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins u2Imm:$u2),
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"$Rdd = combine(#0, #$u2)"> {
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bits<3> Rdd;
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bits<2> u2;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b0;
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let Inst{4-3} = 0b00;
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let Inst{2-0} = Rdd;
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let Inst{6-5} = u2;
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}
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// SA1_combine2i: Combines.
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def V4_SA1_combine2i: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins u2Imm:$u2),
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"$Rdd = combine(#2, #$u2)"> {
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bits<3> Rdd;
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bits<2> u2;
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let Inst{12-10} = 0b111;
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let Inst{8} = 0b0;
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let Inst{4-3} = 0b10;
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let Inst{2-0} = Rdd;
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let Inst{6-5} = u2;
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}
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// SA1_sxtb: Sxtb.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_sxtb: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs),
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"$Rd = sxtb($Rs)"> {
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bits<4> Rd;
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bits<4> Rs;
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let Inst{12-8} = 0b10101;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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}
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// SA1_clrf: Clear if false.
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// SA1_clrf -> SA1_clrfnew
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let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_clrf: SUBInst <
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(outs IntRegs:$Rd),
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(ins ),
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"if (!p0) $Rd = #0"> {
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bits<4> Rd;
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let Inst{12-9} = 0b1101;
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let Inst{6-4} = 0b111;
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let Inst{3-0} = Rd;
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}
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// SL2_loadrb_io: Load byte.
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let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
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def V4_SL2_loadrb_io: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, u3_0Imm:$u3_0),
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"$Rd = memb($Rs + #$u3_0)"> {
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bits<4> Rd;
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bits<4> Rs;
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bits<3> u3_0;
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let Inst{12-11} = 0b10;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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let Inst{10-8} = u3_0;
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}
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// SA1_tfr: Tfr.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_tfr: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs),
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"$Rd = $Rs"> {
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bits<4> Rd;
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bits<4> Rs;
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let Inst{12-8} = 0b10000;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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}
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// SL2_loadrd_sp: Load dword.
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let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
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def V4_SL2_loadrd_sp: SUBInst <
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(outs DoubleRegs:$Rdd),
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(ins u5_3Imm:$u5_3),
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"$Rdd = memd(r29 + #$u5_3)"> {
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bits<3> Rdd;
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bits<8> u5_3;
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|
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let Inst{12-8} = 0b11110;
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let Inst{2-0} = Rdd;
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let Inst{7-3} = u5_3{7-3};
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}
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// SA1_and1: And #1.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_and1: SUBInst <
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs),
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"$Rd = and($Rs, #1)"> {
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bits<4> Rd;
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bits<4> Rs;
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|
|
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let Inst{12-8} = 0b10010;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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}
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|
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// SS2_storebi1: Store byte.
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let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
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def V4_SS2_storebi1: SUBInst <
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(outs ),
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(ins IntRegs:$Rs, u4_0Imm:$u4_0),
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"memb($Rs + #$u4_0)=#1"> {
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bits<4> Rs;
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bits<4> u4_0;
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|
|
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let Inst{12-8} = 0b10011;
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let Inst{7-4} = Rs;
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let Inst{3-0} = u4_0;
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}
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|
|
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// SA1_inc: Inc.
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let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
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def V4_SA1_inc: SUBInst <
|
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(outs IntRegs:$Rd),
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(ins IntRegs:$Rs),
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"$Rd = add($Rs, #1)"> {
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bits<4> Rd;
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|
bits<4> Rs;
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|
|
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let Inst{12-8} = 0b10001;
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let Inst{3-0} = Rd;
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let Inst{7-4} = Rs;
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}
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|
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// SS2_stored_sp: Store dword.
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let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
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def V4_SS2_stored_sp: SUBInst <
|
|
(outs ),
|
|
(ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
|
|
"memd(r29 + #$s6_3) = $Rtt"> {
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|
bits<9> s6_3;
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bits<3> Rtt;
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|
|
|
let Inst{12-9} = 0b0101;
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let Inst{8-3} = s6_3{8-3};
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let Inst{2-0} = Rtt;
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|
}
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|
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// SS2_storew_sp: Store word.
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|
let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
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def V4_SS2_storew_sp: SUBInst <
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|
(outs ),
|
|
(ins u5_2Imm:$u5_2, IntRegs:$Rt),
|
|
"memw(r29 + #$u5_2) = $Rt"> {
|
|
bits<7> u5_2;
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|
bits<4> Rt;
|
|
|
|
let Inst{12-9} = 0b0100;
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let Inst{8-4} = u5_2{6-2};
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let Inst{3-0} = Rt;
|
|
}
|
|
|
|
// SL2_jumpr31_fnew: Indirect conditional jump if false.
|
|
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
|
|
def V4_SL2_jumpr31_fnew: SUBInst <
|
|
(outs ),
|
|
(ins ),
|
|
"if (!p0.new) jumpr:nt r31"> {
|
|
let Inst{12-6} = 0b1111111;
|
|
let Inst{2-0} = 0b111;
|
|
}
|
|
|
|
// SA1_clrt: Clear if true.
|
|
// SA1_clrt -> SA1_clrtnew
|
|
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_clrt: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins ),
|
|
"if (p0) $Rd = #0"> {
|
|
bits<4> Rd;
|
|
|
|
let Inst{12-9} = 0b1101;
|
|
let Inst{6-4} = 0b110;
|
|
let Inst{3-0} = Rd;
|
|
}
|
|
|
|
// SL2_return: Deallocate stack frame and return.
|
|
let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
|
|
def V4_SL2_return: SUBInst <
|
|
(outs ),
|
|
(ins ),
|
|
"dealloc_return"> {
|
|
let Inst{12-6} = 0b1111101;
|
|
let Inst{2} = 0b0;
|
|
}
|
|
|
|
// SA1_dec: Dec.
|
|
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_dec: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs),
|
|
"$Rd = add($Rs,#-1)"> {
|
|
bits<4> Rd;
|
|
bits<4> Rs;
|
|
|
|
let Inst{12-8} = 0b10011;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{7-4} = Rs;
|
|
}
|
|
|
|
// SA1_seti: Set immed.
|
|
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in
|
|
def V4_SA1_seti: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins u6Ext:$u6),
|
|
"$Rd = #$u6"> {
|
|
bits<4> Rd;
|
|
bits<6> u6;
|
|
|
|
let Inst{12-10} = 0b010;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{9-4} = u6;
|
|
}
|
|
|
|
// SL2_jumpr31_t: Indirect conditional jump if true.
|
|
// SL2_jumpr31_t -> SL2_jumpr31_tnew
|
|
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
|
|
def V4_SL2_jumpr31_t: SUBInst <
|
|
(outs ),
|
|
(ins ),
|
|
"if (p0) jumpr r31"> {
|
|
let Inst{12-6} = 0b1111111;
|
|
let Inst{2-0} = 0b100;
|
|
}
|
|
|
|
// SA1_clrfnew: Clear if false.
|
|
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_clrfnew: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins ),
|
|
"if (!p0.new) $Rd = #0"> {
|
|
bits<4> Rd;
|
|
|
|
let Inst{12-9} = 0b1101;
|
|
let Inst{6-4} = 0b101;
|
|
let Inst{3-0} = Rd;
|
|
}
|
|
|
|
// SS1_storew_io: Store word.
|
|
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
|
|
def V4_SS1_storew_io: SUBInst <
|
|
(outs ),
|
|
(ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt),
|
|
"memw($Rs + #$u4_2) = $Rt"> {
|
|
bits<4> Rs;
|
|
bits<6> u4_2;
|
|
bits<4> Rt;
|
|
|
|
let Inst{12} = 0b0;
|
|
let Inst{7-4} = Rs;
|
|
let Inst{11-8} = u4_2{5-2};
|
|
let Inst{3-0} = Rt;
|
|
}
|
|
|
|
// SA1_zxtb: Zxtb.
|
|
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_zxtb: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs),
|
|
"$Rd = and($Rs, #255)"> {
|
|
bits<4> Rd;
|
|
bits<4> Rs;
|
|
|
|
let Inst{12-8} = 0b10111;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{7-4} = Rs;
|
|
}
|
|
|
|
// SA1_addsp: Add.
|
|
let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_addsp: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins u6_2Imm:$u6_2),
|
|
"$Rd = add(r29, #$u6_2)"> {
|
|
bits<4> Rd;
|
|
bits<8> u6_2;
|
|
|
|
let Inst{12-10} = 0b011;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{9-4} = u6_2{7-2};
|
|
}
|
|
|
|
// SL2_loadri_sp: Load word.
|
|
let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SL2_loadri_sp: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins u5_2Imm:$u5_2),
|
|
"$Rd = memw(r29 + #$u5_2)"> {
|
|
bits<4> Rd;
|
|
bits<7> u5_2;
|
|
|
|
let Inst{12-9} = 0b1110;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{8-4} = u5_2{6-2};
|
|
}
|
|
|
|
// SS1_storeb_io: Store byte.
|
|
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
|
|
def V4_SS1_storeb_io: SUBInst <
|
|
(outs ),
|
|
(ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt),
|
|
"memb($Rs + #$u4_0) = $Rt"> {
|
|
bits<4> Rs;
|
|
bits<4> u4_0;
|
|
bits<4> Rt;
|
|
|
|
let Inst{12} = 0b1;
|
|
let Inst{7-4} = Rs;
|
|
let Inst{11-8} = u4_0;
|
|
let Inst{3-0} = Rt;
|
|
}
|
|
|
|
// SL2_return_tnew: Deallocate stack frame and return.
|
|
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
|
|
def V4_SL2_return_tnew: SUBInst <
|
|
(outs ),
|
|
(ins ),
|
|
"if (p0.new) dealloc_return:nt"> {
|
|
let Inst{12-6} = 0b1111101;
|
|
let Inst{2-0} = 0b110;
|
|
}
|
|
|
|
// SL2_return_fnew: Deallocate stack frame and return.
|
|
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
|
|
def V4_SL2_return_fnew: SUBInst <
|
|
(outs ),
|
|
(ins ),
|
|
"if (!p0.new) dealloc_return:nt"> {
|
|
let Inst{12-6} = 0b1111101;
|
|
let Inst{2-0} = 0b111;
|
|
}
|
|
|
|
// SA1_zxth: Zxth.
|
|
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
|
def V4_SA1_zxth: SUBInst <
|
|
(outs IntRegs:$Rd),
|
|
(ins IntRegs:$Rs),
|
|
"$Rd = zxth($Rs)"> {
|
|
bits<4> Rd;
|
|
bits<4> Rs;
|
|
|
|
let Inst{12-8} = 0b10110;
|
|
let Inst{3-0} = Rd;
|
|
let Inst{7-4} = Rs;
|
|
}
|
|
|