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57c57b7739
The access function has a short entry and a short exit, the initialization block is only run the first time. To improve the performance, we want to have a short frame at the entry and exit. We explicitly handle most of the CSRs via copies. Only the CSRs that are not handled via copies will be in CSR_SaveList. Frame lowering and prologue/epilogue insertion will generate a short frame in the entry and exit according to CSR_SaveList. The majority of the CSRs will be handled by register allcoator. Register allocator will try to spill and reload them in the initialization block. We add CSRsViaCopy, it will be explicitly handled during lowering. 1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target supports it for the given machine function and the function has only return exits). We also call TLI->initializeSplitCSR to perform initialization. 2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to virtual registers at beginning of the entry block and copies from virtual registers to CSRsViaCopy at beginning of the exit blocks. 3> we also need to make sure the explicit copies will not be eliminated. The target independent portion was committed as r255353. rdar://problem/23557469 Differential Revision: http://reviews.llvm.org/D15341 llvm-svn: 255821
103 lines
4.1 KiB
C++
103 lines
4.1 KiB
C++
//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
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#define GET_REGINFO_HEADER
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#include "AArch64GenRegisterInfo.inc"
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namespace llvm {
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class MachineFunction;
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class RegScavenger;
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class TargetRegisterClass;
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class Triple;
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struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
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private:
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const Triple &TT;
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public:
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AArch64RegisterInfo(const Triple &TT);
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const MCPhysReg *
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getCalleeSavedRegsViaCopy(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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unsigned getCSRFirstUseCost() const override {
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// The cost will be compared against BlockFrequency where entry has the
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// value of 1 << 14. A value of 5 will choose to spill or split really
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// cold path instead of using a callee-saved register.
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return 5;
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}
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// Calls involved in thread-local variable lookup save more registers than
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// normal calls, so they need a different mask to represent this.
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const uint32_t *getTLSCallPreservedMask() const;
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/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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/// case that 'returned' is on an i64 first argument if the calling convention
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/// is one that can (partially) model this attribute with a preserved mask
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/// (i.e. it is a calling convention that uses the same register for the first
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/// i64 argument and an i64 return value)
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///
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/// Should return NULL in the case that the calling convention does not have
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/// this property
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const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
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int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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unsigned getBaseRegister() const;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif
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