mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
b28a41c23e
Another step for unification llvm assembler/disassembler with sp3. Besides, CodeGen output is a bit improved, thus changes in CodeGen tests. Assembler/Disassembler tests updated/added. Differential Revision: http://reviews.llvm.org/D20796 llvm-svn: 271900
69 lines
2.0 KiB
ArmAsm
69 lines
2.0 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
|
|
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Generic checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
v_mul_i32_i24 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_cndmask_b32 v1, v2, v3
|
|
// CHECK: error: too few operands for instruction
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// _e32 checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Immediate src1
|
|
v_mul_i32_i24_e32 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// sgpr src1
|
|
v_mul_i32_i24_e32 v1, v2, s3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_cndmask_b32_e32 v1, v2, v3, s[0:1]
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// _e64 checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Immediate src0
|
|
v_mul_i32_i24_e64 v1, 100, v3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// Immediate src1
|
|
v_mul_i32_i24_e64 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_add_i32_e32 v1, s[0:1], v2, v3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3]
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, -1
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, s0
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, -1, v2, v3, s0
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e64 v1, s[0:1], v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32 v1, s[0:1], v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// TODO: Constant bus restrictions
|