Alex Bradbury 446ce455bc [RISCV] Add codegen support for atomic load/stores with RV32A ... Fences are inserted according to table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Instruction selection failures will now occur for 8/16/32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch. Differential Revision: https://reviews.llvm.org/D47589 llvm-svn: 334591		2018-06-13 12:04:51 +00:00
..
AsmParser	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
Disassembler	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
InstPrinter	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
MCTargetDesc	Fix compilation of WebAssembly and RISCV after r334078	2018-06-06 10:57:50 +00:00
TargetInfo
CMakeLists.txt	[RISCV] Tablegen-driven Instruction Compression.	2018-04-06 21:07:05 +00:00
LLVMBuild.txt
RISCV.h
RISCV.td	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVCallingConv.td
RISCVFrameLowering.cpp	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVFrameLowering.h	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVInstrFormats.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVInstrInfo.h	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVInstrInfoA.td	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVInstrInfoC.td	[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0	2018-04-12 19:22:40 +00:00
RISCVInstrInfoD.td	[RISCV] Codegen support for RV32D floating point comparison operations	2018-04-12 05:50:06 +00:00
RISCVInstrInfoF.td	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfoM.td	[RISCV] Codegen support for the standard RV32M instruction set extension	2018-01-18 12:36:38 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Add peepholes for Global Address lowering patterns	2018-05-29 19:34:54 +00:00
RISCVISelLowering.cpp	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVISelLowering.h	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv	2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVRegisterInfo.cpp	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp	[RISCV] Codegen support for atomic operations on RV32I	2018-06-13 11:58:46 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00