Benjamin Kramer 26eae94ea6 X86: Add patterns for X86ISD::VSEXT in registers. ... Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. llvm-svn: 172353		2013-01-13 11:37:04 +00:00
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ARM	Simplify writing floating types to assembly.	2013-01-11 10:36:13 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon
MBlaze
Mips	[mips] MipsTargetLowering::getSetCCResultType should return a vector type if	2013-01-04 20:06:01 +00:00
MSP430
NVPTX
PowerPC	When lowering an inreg sext first shift left, then right arithmetically.	2013-01-12 19:06:44 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	X86: Add patterns for X86ISD::VSEXT in registers.	2013-01-13 11:37:04 +00:00
XCore