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24ba078dcd
The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
36 lines
1.0 KiB
ArmAsm
36 lines
1.0 KiB
ArmAsm
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
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; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
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foo:
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sbis 4, 3
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sbis 6, 2
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sbis 16, 5
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sbis 0, 0
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sbis 31, 0
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sbis 0, 7
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sbis 31, 7
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sbis FOO+4, 7
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; CHECK: sbis 4, 3 ; encoding: [0x23,0x9b]
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; CHECK: sbis 6, 2 ; encoding: [0x32,0x9b]
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; CHECK: sbis 16, 5 ; encoding: [0x85,0x9b]
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; CHECK: sbis 0, 0 ; encoding: [0x00,0x9b]
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; CHECK: sbis 31, 0 ; encoding: [0xf8,0x9b]
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; CHECK: sbis 0, 7 ; encoding: [0x07,0x9b]
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; CHECK: sbis 31, 7 ; encoding: [0xff,0x9b]
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; CHECK: sbis FOO+4, 7 ; encoding: [0bAAAAA111,0x9b]
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; CHECK: ; fixup A - offset: 0, value: FOO+4, kind: fixup_port5
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; CHECK-INST: sbis 4, 3
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; CHECK-INST: sbis 6, 2
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; CHECK-INST: sbis 16, 5
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; CHECK-INST: sbis 0, 0
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; CHECK-INST: sbis 31, 0
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; CHECK-INST: sbis 0, 7
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; CHECK-INST: sbis 31, 7
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; CHECK-INST: sbis 0, 7
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