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llvm-mirror/test/CodeGen/Hexagon/bit-gen-rseq.ll
Brendon Cahoon e37295579e MachinePipeliner pass that implements Swing Modulo Scheduling
Software pipelining is an optimization for improving ILP by
overlapping loop iterations. Swing Modulo Scheduling (SMS) is
an implementation of software pipelining that attempts to
reduce register pressure and generate efficient pipelines with
a low compile-time cost.

This implementaion of SMS is a target-independent back-end pass.
When enabled, the pass should run just prior to the register
allocation pass, while the machine IR is in SSA form. If the pass
is successful, then the original loop is replaced by the optimized
loop. The optimized loop contains one or more prolog blocks, the
pipelined kernel, and one or more epilog blocks.

This pass is enabled for Hexagon only. To enable for other targets,
a couple of target specific hooks must be implemented, and the
pass needs to be called from the target's TargetMachine
implementation.

Differential Review: http://reviews.llvm.org/D16829

llvm-svn: 277169
2016-07-29 16:44:44 +00:00

44 lines
2.0 KiB
LLVM

; RUN: llc -march=hexagon -disable-hsdr -hexagon-subreg-liveness < %s | FileCheck %s
; Check that we don't generate any bitwise operations.
; CHECK-NOT: = or(
; CHECK-NOT: = and(
target triple = "hexagon"
define i32 @fred(i32* nocapture readonly %p, i32 %n) #0 {
entry:
%t.sroa.0.048 = load i32, i32* %p, align 4
%cmp49 = icmp ugt i32 %n, 1
br i1 %cmp49, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%t.sroa.0.052 = phi i32 [ %t.sroa.0.0, %for.body ], [ %t.sroa.0.048, %entry ]
%t.sroa.11.051 = phi i64 [ %t.sroa.11.0.extract.shift, %for.body ], [ 0, %entry ]
%i.050 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
%t.sroa.0.0.insert.ext = zext i32 %t.sroa.0.052 to i64
%t.sroa.0.0.insert.insert = or i64 %t.sroa.0.0.insert.ext, %t.sroa.11.051
%0 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert, i64 %t.sroa.0.0.insert.insert)
%t.sroa.11.0.extract.shift = and i64 %0, -4294967296
%arrayidx4 = getelementptr inbounds i32, i32* %p, i32 %i.050
%inc = add nuw i32 %i.050, 1
%t.sroa.0.0 = load i32, i32* %arrayidx4, align 4
%exitcond = icmp eq i32 %inc, %n
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
%t.sroa.0.0.lcssa = phi i32 [ %t.sroa.0.048, %entry ], [ %t.sroa.0.0, %for.body ]
%t.sroa.11.0.lcssa = phi i64 [ 0, %entry ], [ %t.sroa.11.0.extract.shift, %for.body ]
%t.sroa.0.0.insert.ext17 = zext i32 %t.sroa.0.0.lcssa to i64
%t.sroa.0.0.insert.insert19 = or i64 %t.sroa.0.0.insert.ext17, %t.sroa.11.0.lcssa
%1 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert19, i64 %t.sroa.0.0.insert.insert19)
%t.sroa.11.0.extract.shift41 = lshr i64 %1, 32
%t.sroa.11.0.extract.trunc42 = trunc i64 %t.sroa.11.0.extract.shift41 to i32
ret i32 %t.sroa.11.0.extract.trunc42
}
declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
attributes #0 = { norecurse nounwind readonly }
attributes #1 = { nounwind readnone }