| .. |
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autohvx
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[Hexagon] Generate valignb for shifting shuffles (instead of vdelta)
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2018-03-02 22:22:19 +00:00 |
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intrinsics
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[Hexagon] Fix operand-swapping PatFrag for atomic stores
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2017-12-15 20:13:57 +00:00 |
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loop-idiom
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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vect
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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absaddr-store.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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absimm.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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addaddi.ll
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[Hexagon] Add extra pattern for S4_addaddi
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2017-10-23 19:07:50 +00:00 |
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adde.ll
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addh-sext-trunc.ll
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addh-shifted.ll
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addh.ll
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addr-calc-opt.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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addrmode-globoff.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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addrmode-indoff.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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addrmode-keepdeadphis.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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addrmode-rr-to-io.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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adjust-latency-stackST.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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alu64.ll
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always-ext.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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anti-dep-partial.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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args.ll
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ashift-left-right.ll
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Atomics.ll
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avoid-predspill-calleesaved.ll
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avoid-predspill.ll
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bank-conflict-load.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-addr-align.mir
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[Hexagon] Fix alignment calculation of stack objects in Hexagon bit tracker
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2018-02-20 14:29:43 +00:00 |
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bit-bitsplit-at.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-bitsplit-src.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-bitsplit.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-eval.ll
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bit-ext-sat.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extract-off.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extract.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-extractu-half.ll
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bit-gen-rseq.ll
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bit-has.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-loop-rc-mismatch.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-loop.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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bit-phi.ll
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bit-rie.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bit-skip-byval.ll
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bit-validate-reg.ll
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bit-visit-flowq.ll
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bitconvert-vector.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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bitmanip.ll
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block-addr.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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block-ranges-nodef.ll
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branch-folder-hoist-kills.mir
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[CodeGen] Unify the syntax of MBB liveins in MIR and -debug output
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2018-02-09 01:14:44 +00:00 |
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branch-non-mbb.ll
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branchfolder-insert-impdef.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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branchfolder-keep-impdef.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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BranchPredict.ll
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brev_ld.ll
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brev_st.ll
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bugAsmHWloop.ll
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build-vector-shuffle.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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build-vector-v4i8-zext.ll
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[Hexagon] Make sure to zero-extend bytes before building a vector
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2017-11-28 19:13:17 +00:00 |
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builtin-expect.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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builtin-prefetch-offset.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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builtin-prefetch.ll
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call-ret-i1.ll
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[Hexagon] Return the correct chain edge for i1 function calls
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2017-10-23 19:35:25 +00:00 |
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calling-conv-2.ll
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callr-dep-edge.ll
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cext-check.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cext-opt-basic.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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cext-opt-numops.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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cext-opt-range-assert.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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cext-opt-range-offset.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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cext-opt-shifted-range.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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cext-valid-packet1.ll
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cext-valid-packet2.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cext.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cexti16.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cfgopt-fall-through.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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cfi-late.ll
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cfi-offset.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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checktabs.ll
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circ_ld.ll
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circ_ldd_bug.ll
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[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
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2017-11-30 12:12:19 +00:00 |
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circ_ldw.ll
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circ_st.ll
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circ-load-isel.ll
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clr_set_toggle.ll
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cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cmp-to-predreg.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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cmp.ll
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cmpb_pred.ll
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cmpb-dec-imm.ll
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[Hexagon] Add patterns for cmpb/cmph with immediate arguments
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2017-10-13 15:43:12 +00:00 |
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cmpb-eq.ll
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cmph-gtu.ll
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[Hexagon] Add patterns for cmpb/cmph with immediate arguments
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2017-10-13 15:43:12 +00:00 |
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combine_ir.ll
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combine.ll
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common-gep-basic.ll
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common-gep-icm.ll
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common-gep-inbounds.ll
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[Hexagon] Run late copy propagation and dead code elimination passes
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2018-01-24 17:48:11 +00:00 |
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compound.ll
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const64.ll
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const-pool-tf.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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constp-andir-global.mir
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[Hexagon] Recognize non-immediate constants in HexagonConstPropagation
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2018-02-23 20:33:26 +00:00 |
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constp-clb.ll
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constp-combine-neg.ll
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[Hexagon] Implement buildVector32 and buildVector64 as utility functions
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2017-11-22 20:56:23 +00:00 |
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constp-ctb.ll
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constp-extract.ll
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constp-physreg.ll
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constp-rewrite-branches.ll
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constp-rseq.ll
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constp-vsplat.ll
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convert_const_i1_to_i8.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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convert-to-dot-old.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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convertdptoint.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertdptoll.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertsptoint.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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convertsptoll.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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copy-to-combine-dbg.ll
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csr-func-usedef.ll
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ctor.ll
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dadd.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dead-store-stack.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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dmul.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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double.ll
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doubleconvert-ieee-rnd-near.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dsub.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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dualstore.ll
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duplex-addi-global-imm.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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duplex.ll
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[CodeGen] Always use printReg to print registers in both MIR and debug
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2017-11-30 16:12:24 +00:00 |
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early-if-conversion-bug1.ll
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Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
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2018-01-19 17:13:12 +00:00 |
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early-if-debug.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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early-if-low8.mir
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[Hexagon] Handle *Low8 register classes in early if-conversion
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2018-02-20 18:19:17 +00:00 |
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early-if-merge-loop.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if-phi-i1.ll
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early-if-spare.ll
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early-if-vecpi.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if-vecpred.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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early-if.ll
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eh_return.ll
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eliminate-pred-spill.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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expand-condsets-basic.ll
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expand-condsets-dead-bad.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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expand-condsets-dead-pred.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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expand-condsets-def-undef.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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expand-condsets-extend.ll
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expand-condsets-imm.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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expand-condsets-impuse.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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expand-condsets-pred-undef.ll
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expand-condsets-rm-reg.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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expand-condsets-undef2.ll
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expand-condsets-undef.ll
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expand-condsets-undefvni.ll
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Missed a check for UndefVI in r306466
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2017-06-28 15:46:16 +00:00 |
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expand-vselect-kill.ll
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[Hexagon] Run late copy propagation and dead code elimination passes
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2018-01-24 17:48:11 +00:00 |
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expand-vstorerw-undef2.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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expand-vstorerw-undef.ll
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[Hexagon] Allow construction of HVX vector predicates
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2017-12-20 20:49:43 +00:00 |
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extload-combine.ll
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extract-basic.ll
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fadd.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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fcmp.ll
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find-loop-instr.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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fixed-spill-mutable.ll
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float-amode.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fminmax.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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fmul.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
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2017-07-05 13:08:03 +00:00 |
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fpelim-basic.ll
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[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer
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2017-06-30 21:21:40 +00:00 |
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frame-offset-overflow.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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fsel.ll
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fsub.ll
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[Hexagon] Preclude non-memory test from being optimized away. NFC.
|
2017-07-05 13:08:03 +00:00 |
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fusedandshift.ll
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gp-plus-offset-load.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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gp-plus-offset-store.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
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gp-rel.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
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hasfp-crash1.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hasfp-crash2.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hexagon_vector_loop_carried_reuse_constant.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hexagon_vector_loop_carried_reuse.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hvx-nontemporal.ll
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[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hwloop1.ll
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hwloop2.ll
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hwloop3.ll
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hwloop4.ll
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hwloop5.ll
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hwloop-cleanup.ll
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hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
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hwloop-le.ll
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hwloop-loop1.ll
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[Hexagon] Reorganize and update instruction patterns
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2017-10-20 19:33:12 +00:00 |
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll
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[Hexagon] New HVX target features.
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2017-10-18 18:07:07 +00:00 |
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
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[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-redef-imm.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
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2018-01-31 22:04:26 +00:00 |
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hwloop-wrap2.ll
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hwloop-wrap.ll
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i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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idxload-with-zero-offset.ll
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[Hexagon] Remove {{ *}} from testcases
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2018-03-06 19:07:21 +00:00 |
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ifcvt-common-kill.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
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ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
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ifcvt-edge-weight.ll
|
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
|
2018-02-09 00:10:31 +00:00 |
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ifcvt-impuse-livein.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
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ifcvt-live-subreg.mir
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Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
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ifcvt-simple-bprob.ll
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indirect-br.ll
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inline-asm-a.ll
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[Hexagon] Add inline-asm constraint 'a' for modifier register class
|
2017-07-21 17:51:27 +00:00 |
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inline-asm-bad-constraint.ll
|
[Hexagon] Report error instead of crashing on wrong inline-asm constraints
|
2017-10-20 20:24:44 +00:00 |
|
inline-asm-hexagon.ll
|
|
|
|
inline-asm-i1.ll
|
|
|
|
inline-asm-qv.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
inline-asm-vecpred128.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
insert4.ll
|
|
|
|
insert-basic.ll
|
|
|
|
invalid-dotnew-attempt.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
is-legal-void.ll
|
|
|
|
isel-combine-half.ll
|
[Hexagon] Add patterns to select A2_combine_ll and its variants
|
2017-11-22 20:55:41 +00:00 |
|
isel-exti1.ll
|
|
|
|
isel-global-offset-alignment.ll
|
Revert: [Hexagon] Make sure that offset on globals matches alignment requirements
|
2018-01-30 18:10:27 +00:00 |
|
isel-i1arg-crash.ll
|
|
|
|
isel-op-zext-i1.ll
|
|
|
|
isel-prefer.ll
|
[Hexagon] Add patterns to select A2_combine_ll and its variants
|
2017-11-22 20:55:41 +00:00 |
|
isel-setcc-i1.ll
|
[Hexagon] Add patterns for compares of i1 values
|
2018-02-27 18:31:46 +00:00 |
|
isel-simplify-crash.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
isel-vacopy.ll
|
[Hexagon] Handle VACOPY in isel lowering
|
2018-03-02 18:35:57 +00:00 |
|
jt-in-text.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
lit.local.cfg
|
|
|
|
livephysregs-add-pristines.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
livephysregs-lane-masks2.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
livephysregs-lane-masks.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
loadi1-G0.ll
|
|
|
|
loadi1-v4-G0.ll
|
|
|
|
loadi1-v4.ll
|
|
|
|
loadi1.ll
|
|
|
|
long-calls.ll
|
|
|
|
loop-prefetch.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
lower-extract-subvector.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
macint.ll
|
|
|
|
maxd.ll
|
|
|
|
maxh.ll
|
|
|
|
maxud.ll
|
|
|
|
maxuw.ll
|
|
|
|
maxw.ll
|
|
|
|
mem-fi-add.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
memcpy-likely-aligned.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
memops1.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
memops2.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
memops3.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
memops-stack.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
memops.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
mind.ll
|
|
|
|
minu-zext-8.ll
|
|
|
|
minu-zext-16.ll
|
|
|
|
minud.ll
|
|
|
|
minuw.ll
|
|
|
|
minw.ll
|
|
|
|
misaligned_double_vector_store_not_fast.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
misaligned-access.ll
|
|
|
|
misched-top-rptracker-sync.ll
|
|
|
|
mpy.ll
|
|
|
|
mul64-sext.ll
|
[Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiply
|
2018-02-27 22:44:41 +00:00 |
|
mulh.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
mulhs.ll
|
|
|
|
multi-cycle.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
mux-basic.ll
|
|
|
|
mux-kill1.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
mux-kill2.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
mux-kill3.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
mux-undef.ll
|
[Hexagon] Skip mux generation when predicate register is undefined
|
2017-06-08 20:56:36 +00:00 |
|
newify-crash.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
newvaluejump2.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
newvaluejump3.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
newvaluejump-c4.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
newvaluejump-float.mir
|
[Hexagon] Don't form new-value jumps from floating-point instructions
|
2018-02-06 19:08:41 +00:00 |
|
newvaluejump-kill2.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
newvaluejump-kill.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
newvaluejump-solo.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
newvaluejump.ll
|
|
|
|
newvalueSameReg.ll
|
|
|
|
newvaluestore.ll
|
|
|
|
NVJumpCmp.ll
|
|
|
|
opt-addr-mode.ll
|
|
|
|
opt-fabs.ll
|
|
|
|
opt-fneg.ll
|
|
|
|
opt-spill-volatile.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
packetize_cond_inst.ll
|
|
|
|
packetize-cfi-location.ll
|
|
|
|
packetize-load-store-aliasing.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
packetize-nvj-no-prune.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
packetize-return-arg.ll
|
|
|
|
packetize-tailcall-arg.ll
|
|
|
|
peephole-kill-flags.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
peephole-op-swap.ll
|
|
|
|
pic-jumptables.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
pic-local.ll
|
|
|
|
pic-regusage.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
pic-simple.ll
|
|
|
|
pic-static.ll
|
|
|
|
plt-rel.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
post-inc-aa-metadata.ll
|
[CodeGen] Don't omit any redundant information in -debug output
|
2018-02-26 15:23:42 +00:00 |
|
post-ra-kill-update.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
postinc-baseoffset.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
postinc-load.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
postinc-offset.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
postinc-store.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
PR33749.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
pred-absolute-store.ll
|
[Hexagon] Return true in enableMultipleCopyHints().
|
2018-02-21 16:37:45 +00:00 |
|
pred-gp.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
pred-instrs.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
predicate-copy.ll
|
|
|
|
predicate-logical.ll
|
|
|
|
predicate-rcmp.ll
|
|
|
|
propagate-vcombine.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-copy-renamable-reserved.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
rdf-copy-undef2.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
rdf-copy.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
rdf-cover-use.ll
|
[RDF] Remove covered parts of reached uses for phi and use in same block
|
2017-05-05 22:10:32 +00:00 |
|
rdf-dead-loop.ll
|
|
|
|
rdf-def-mask.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-ehlabel-live.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
rdf-extra-livein.ll
|
|
|
|
rdf-filter-defs.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
rdf-ignore-undef.ll
|
|
|
|
rdf-inline-asm-fixed.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-inline-asm.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
rdf-multiple-phis-up.ll
|
|
|
|
rdf-phi-shadows.ll
|
|
|
|
rdf-phi-up.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
rdf-reset-kills.ll
|
|
|
|
readcyclecounter.ll
|
|
|
|
reg-scavengebug-3.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
reg-scavenger-valid-slot.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
regalloc-bad-undef.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
regalloc-block-overlap.ll
|
[Hexagon] Run late copy propagation and dead code elimination passes
|
2018-01-24 17:48:11 +00:00 |
|
regalloc-liveout-undef.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
relax.ll
|
|
|
|
remove_lsr.ll
|
|
|
|
remove-endloop.ll
|
|
|
|
restore-single-reg.ll
|
|
|
|
ret-struct-by-val.ll
|
|
|
|
runtime-stkchk.ll
|
Add address space mangling to lifetime intrinsics
|
2017-04-10 20:18:21 +00:00 |
|
sdata-array.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
sdata-basic.ll
|
|
|
|
sdr-basic.ll
|
|
|
|
sdr-shr32.ll
|
|
|
|
section_7275.ll
|
|
|
|
select-instr-align.ll
|
[Hexagon] Split HVX vector pair loads/stores, expand unaligned loads
|
2018-02-14 20:46:06 +00:00 |
|
sf-min-max.ll
|
|
|
|
sffms.ll
|
|
|
|
shrink-frame-basic.ll
|
|
|
|
signed_immediates.ll
|
|
|
|
simple_addend.ll
|
|
|
|
simpletailcall.ll
|
|
|
|
split-const32-const64.ll
|
[Hexagon] Remove trailing spaces, NFC
|
2017-11-22 20:43:00 +00:00 |
|
stack-align1.ll
|
|
|
|
stack-align2.ll
|
|
|
|
stack-align-reset.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
stack-alloca1.ll
|
|
|
|
stack-alloca2.ll
|
|
|
|
static.ll
|
|
|
|
store-imm-amode.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
store-imm-large-stack.ll
|
[Hexagon] Recognize potential offset overflow for store-imm to stack
|
2017-06-22 14:11:23 +00:00 |
|
store-imm-stack-object.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
store-shift.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
store-widen-aliased-load.ll
|
|
|
|
store-widen-negv2.ll
|
|
|
|
store-widen-negv.ll
|
|
|
|
store-widen.ll
|
|
|
|
storerd-io-over-rr.ll
|
|
|
|
storerinewabs.ll
|
|
|
|
struct_args_large.ll
|
|
|
|
struct_args.ll
|
|
|
|
sube.ll
|
|
|
|
subi-asl.ll
|
|
|
|
SUnit-boundary-prob.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-explicit-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-function-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-multiple-functions.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
switch-lut-text-section.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
swp-const-tc.ll
|
[LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()
|
2017-08-09 11:28:01 +00:00 |
|
swp-dag-phi.ll
|
|
|
|
swp-epilog-phi10.ll
|
|
|
|
swp-epilog-reuse-1.ll
|
[NFC] fix trivial typos in comments
|
2018-01-24 05:04:35 +00:00 |
|
swp-epilog-reuse.ll
|
|
|
|
swp-matmul-bitext.ll
|
[Hexagon] Use automatically-generated scheduling information for HVX
|
2017-05-03 20:10:36 +00:00 |
|
swp-max.ll
|
|
|
|
swp-multi-loops.ll
|
|
|
|
swp-order-copies.ll
|
[Pipeliner] Improve serialization order for post-increments
|
2017-10-11 15:51:44 +00:00 |
|
swp-prolog-phi4.ll
|
|
|
|
swp-stages4.ll
|
[Pipeliner] Drop memrefs instead of creating ones with size UINT64_MAX
|
2018-02-27 22:40:52 +00:00 |
|
swp-stages5.ll
|
|
|
|
swp-vect-dotprod.ll
|
|
|
|
swp-vmult.ll
|
|
|
|
swp-vsum.ll
|
|
|
|
tail-call-mem-intrinsics.ll
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
tail-call-trunc.ll
|
|
|
|
tail-dup-subreg-abort.ll
|
|
|
|
tail-dup-subreg-map.ll
|
[DAG] make binops with undef operands consistent with IR
|
2018-02-12 21:37:27 +00:00 |
|
tailcall_fastcc_ccc.ll
|
|
|
|
target-flag-ext.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
tfr-to-combine.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
tls_pic.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
tls_static.ll
|
[Hexagon] Reorganize and update instruction patterns
|
2017-10-20 19:33:12 +00:00 |
|
trap-unreachable.ll
|
[CodeGen] Add a -trap-unreachable option for debugging
|
2018-02-12 11:06:27 +00:00 |
|
two-crash.ll
|
|
|
|
undo-dag-shift.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
union-1.ll
|
|
|
|
unreachable-mbb-phi-subreg.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
usr-ovf-dep.ll
|
|
|
|
v6vec-vprint.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60-cur.ll
|
[Hexagon] Allow construction of HVX vector predicates
|
2017-12-20 20:49:43 +00:00 |
|
v60-vsel1.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60Intrins.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60small.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
v60Vasr.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vaddh.ll
|
|
|
|
validate-offset.ll
|
|
|
|
vararg-formal.ll
|
[Hexagon] Fix lowering of formal arguments after r324737
|
2018-02-15 15:47:53 +00:00 |
|
vassign-to-combine.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vdmpy-halide-test.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vec-pred-spill1.ll
|
[Hexagon] Remove {{ *}} from testcases
|
2018-03-06 19:07:21 +00:00 |
|
vec-vararg-align.ll
|
[Hexagon] Express calling conventions via .td file instead of hand-coding
|
2018-02-09 15:30:02 +00:00 |
|
vector-align.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vector-ext-load.ll
|
|
|
|
vextract-basic.mir
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
vload-postinc-sel.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vmpa-halide-test.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vpack_eo.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vselect-pseudo.ll
|
[Hexagon] New HVX target features.
|
2017-10-18 18:07:07 +00:00 |
|
vsplat-isel.ll
|
|
|
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zextloadi1.ll
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[Hexagon] Minimize number of repeated constant extenders
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2017-10-13 19:02:59 +00:00 |
