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llvm-mirror/test/CodeGen/Hexagon/builtin-expect.ll
Sumanth Gundapaneni 262321d1ff [Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Differential Revision: https://reviews.llvm.org/D38851

llvm-svn: 316101
2017-10-18 18:07:07 +00:00

45 lines
1.3 KiB
LLVM

; RUN: llc -march=hexagon -disable-block-placement < %s | FileCheck %s
; Check that the branch to the block b10 is marked as taken (i.e. ":t").
; CHECK-LABEL: foo
; CHECK: if ({{.*}}) jump:t .LBB0_[[LAB:[0-9]+]]
; CHECK: [[LAB]]:
; CHECK: add({{.*}},#65)
target triple = "hexagon"
define i32 @foo(i32 %a0) local_unnamed_addr #0 {
b1:
%v2 = icmp eq i32 %a0, 0
br i1 %v2, label %b3, label %b10, !prof !0
b3: ; preds = %b1
br label %b4
b4: ; preds = %b4, %b3
%v5 = phi i32 [ %v6, %b4 ], [ 0, %b3 ]
%v6 = add nuw nsw i32 %v5, 1
%v7 = mul nuw nsw i32 %v5, 67
%v8 = tail call i32 @bar(i32 %v7) #0
%v9 = icmp eq i32 %v6, 10
br i1 %v9, label %b13, label %b4
b10: ; preds = %b1
%v11 = add nsw i32 %a0, 65
%v12 = tail call i32 @bar(i32 %v11) #0
br label %b14
b13: ; preds = %b4
br label %b14
b14: ; preds = %b13, %b10
%v15 = phi i32 [ %v12, %b10 ], [ 0, %b13 ]
ret i32 %v15
}
declare i32 @bar(i32) local_unnamed_addr #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" }
!0 = !{!"branch_weights", i32 1, i32 2000}