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97babd4ccf
Summary: On XMEGA, I/O address space is same as data address space - there is no 0x20 offset, because CPU General Purpose Registers are not mapped in data address space. From https://en.wikipedia.org/wiki/AVR_microcontrollers > In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: hiraditya, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77207 Patch by Vlastimil Labsky.
58 lines
2.0 KiB
C++
58 lines
2.0 KiB
C++
//===-- AVRSubtarget.cpp - AVR Subtarget Information ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AVR specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRSubtarget.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "AVR.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#define DEBUG_TYPE "avr-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "AVRGenSubtargetInfo.inc"
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namespace llvm {
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AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const AVRTargetMachine &TM)
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: AVRGenSubtargetInfo(TT, CPU, FS), ELFArch(0),
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// Subtarget features
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m_hasSRAM(false), m_hasJMPCALL(false), m_hasIJMPCALL(false),
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m_hasEIJMPCALL(false), m_hasADDSUBIW(false), m_hasSmallStack(false),
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m_hasMOVW(false), m_hasLPM(false), m_hasLPMX(false), m_hasELPM(false),
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m_hasELPMX(false), m_hasSPM(false), m_hasSPMX(false), m_hasDES(false),
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m_supportsRMW(false), m_supportsMultiplication(false), m_hasBREAK(false),
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m_hasTinyEncoding(false), m_hasMemMappedGPR(false),
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m_FeatureSetDummy(false),
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InstrInfo(), FrameLowering(),
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TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
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// Parse features string.
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ParseSubtargetFeatures(CPU, FS);
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}
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AVRSubtarget &
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AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine &TM) {
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// Parse features string.
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ParseSubtargetFeatures(CPU, FS);
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return *this;
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}
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} // end of namespace llvm
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