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a8d108687b
As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
110 lines
4.5 KiB
LLVM
110 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X64
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define double @mmx_zero(double, double, double, double) nounwind {
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; X86-LABEL: mmx_zero:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $16, %esp
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; X86-NEXT: movq 8(%ebp), %mm0
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; X86-NEXT: movq 16(%ebp), %mm5
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; X86-NEXT: movq %mm5, (%esp) # 8-byte Spill
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; X86-NEXT: movq %mm0, %mm3
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; X86-NEXT: paddd %mm5, %mm3
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; X86-NEXT: pxor %mm1, %mm1
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; X86-NEXT: movq %mm3, %mm6
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; X86-NEXT: pmuludq %mm1, %mm6
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; X86-NEXT: movq 24(%ebp), %mm4
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; X86-NEXT: movq %mm6, %mm2
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; X86-NEXT: paddd %mm4, %mm2
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; X86-NEXT: paddw %mm2, %mm0
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; X86-NEXT: movq %mm5, %mm1
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; X86-NEXT: paddw %mm0, %mm1
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; X86-NEXT: movq 32(%ebp), %mm5
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; X86-NEXT: movq %mm1, %mm7
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; X86-NEXT: pmuludq %mm5, %mm7
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; X86-NEXT: paddw %mm4, %mm7
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; X86-NEXT: paddw %mm7, %mm5
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; X86-NEXT: paddw %mm5, %mm2
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; X86-NEXT: paddw %mm2, %mm0
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; X86-NEXT: paddw %mm6, %mm0
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; X86-NEXT: pmuludq %mm3, %mm0
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; X86-NEXT: paddw {{\.LCPI.*}}, %mm0
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; X86-NEXT: paddw %mm1, %mm0
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; X86-NEXT: pmuludq %mm7, %mm0
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; X86-NEXT: pmuludq (%esp), %mm0 # 8-byte Folded Reload
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; X86-NEXT: paddw %mm5, %mm0
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; X86-NEXT: paddw %mm2, %mm0
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; X86-NEXT: movq2dq %mm0, %xmm0
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; X86-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
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; X86-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: mmx_zero:
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; X64: # %bb.0:
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; X64-NEXT: movdq2q %xmm0, %mm0
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; X64-NEXT: movdq2q %xmm1, %mm5
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; X64-NEXT: movq %mm5, -{{[0-9]+}}(%rsp) # 8-byte Spill
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; X64-NEXT: movq %mm0, %mm3
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; X64-NEXT: paddd %mm5, %mm3
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; X64-NEXT: pxor %mm1, %mm1
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; X64-NEXT: movq %mm3, %mm6
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; X64-NEXT: pmuludq %mm1, %mm6
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; X64-NEXT: movdq2q %xmm2, %mm4
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; X64-NEXT: movq %mm6, %mm2
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; X64-NEXT: paddd %mm4, %mm2
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; X64-NEXT: paddw %mm2, %mm0
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; X64-NEXT: movq %mm5, %mm1
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; X64-NEXT: paddw %mm0, %mm1
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; X64-NEXT: movdq2q %xmm3, %mm5
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; X64-NEXT: movq %mm1, %mm7
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; X64-NEXT: pmuludq %mm5, %mm7
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; X64-NEXT: paddw %mm4, %mm7
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; X64-NEXT: paddw %mm7, %mm5
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; X64-NEXT: paddw %mm5, %mm2
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; X64-NEXT: paddw %mm2, %mm0
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; X64-NEXT: paddw %mm6, %mm0
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; X64-NEXT: pmuludq %mm3, %mm0
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; X64-NEXT: paddw {{\.LCPI.*}}, %mm0
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; X64-NEXT: paddw %mm1, %mm0
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; X64-NEXT: pmuludq %mm7, %mm0
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; X64-NEXT: pmuludq -{{[0-9]+}}(%rsp), %mm0 # 8-byte Folded Reload
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; X64-NEXT: paddw %mm5, %mm0
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; X64-NEXT: paddw %mm2, %mm0
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; X64-NEXT: movq2dq %mm0, %xmm0
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; X64-NEXT: retq
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%5 = bitcast double %0 to x86_mmx
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%6 = bitcast double %1 to x86_mmx
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%7 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %5, x86_mmx %6)
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%8 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %7, x86_mmx bitcast (double 0.000000e+00 to x86_mmx))
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%9 = bitcast double %2 to x86_mmx
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%10 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %8, x86_mmx %9)
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%11 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %5, x86_mmx %10)
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%12 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %6, x86_mmx %11)
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%13 = bitcast double %3 to x86_mmx
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%14 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %12, x86_mmx %13)
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%15 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %14, x86_mmx %9)
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%16 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %15, x86_mmx %13)
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%17 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %16, x86_mmx %10)
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%18 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %17, x86_mmx %11)
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%19 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %18, x86_mmx %8)
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%20 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %19, x86_mmx %7)
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%21 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %20, x86_mmx bitcast (double 0.000000e+00 to x86_mmx))
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%22 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %21, x86_mmx %12)
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%23 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %22, x86_mmx %15)
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%24 = tail call x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx %23, x86_mmx %6)
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%25 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %24, x86_mmx %16)
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%26 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %25, x86_mmx %17)
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%27 = bitcast x86_mmx %26 to double
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ret double %27
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}
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declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx)
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