1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
llvm-mirror/test/CodeGen/X86/physreg-pairs-error.ll
Nirav Dave b389549f08 [X86] Fix register resizings for inline assembly register operands.
When replacing a named register input to the appropriately sized
sub/super-register. In the case of a 64-bit value being assigned to a
register in 32-bit mode, match GCC's assignment.

Reviewers: eli.friedman, craig.topper

Subscribers: nickdesaulniers, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D51502

llvm-svn: 342175
2018-09-13 20:33:56 +00:00

13 lines
444 B
LLVM

; RUN: not llc -mtriple=i386-unknown-linux-gnu -o - %s 2>&1 | FileCheck %s
; CHECK: error: couldn't allocate input reg for constraint '{esp}'
define dso_local i64 @test_esp(i64 %in) local_unnamed_addr nounwind {
entry:
%0 = tail call i64 asm sideeffect "mov $1, $0", "=r,{esp},~{dirflag},~{fpsr},~{flags}"(i64 81985529216486895)
%conv = trunc i64 %0 to i32
%add = add nsw i32 %conv, 3
%conv1 = sext i32 %add to i64
ret i64 %conv1
}