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Matthias Braun aee5f0fc5d Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
  of going through the whole codegen pipeline.

This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.

llvm-svn: 345532
2018-10-29 20:10:42 +00:00

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LLVM

; ; RUN: llc < %s -mtriple=i686-pc-linux -O0 | FileCheck %s
declare void @g(i32, i1)
;CHECK-LABEL: f:
;CHECK: cmpxchg8b
;CHECK: sete [[REG:%[abcd]l]]
;CHECK: movzbl [[REG]]
define void @f(i64* %arg, i64 %arg1) {
entry:
%tmp5 = cmpxchg i64* %arg, i64 %arg1, i64 %arg1 seq_cst seq_cst
%tmp7 = extractvalue { i64, i1 } %tmp5, 1
%tmp9 = zext i1 %tmp7 to i32
call void @g(i32 %tmp9, i1 %tmp7)
ret void
}