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cb2d622c70
We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
108 lines
3.4 KiB
LLVM
108 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse2-builtins.c
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define i64 @test_mm_cvtsd_si64(<2 x double> %a0) nounwind {
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; SSE-LABEL: test_mm_cvtsd_si64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtsd2si %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_cvtsd_si64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtsd2si %xmm0, %rax
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; AVX-NEXT: retq
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%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
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define i64 @test_mm_cvtsi128_si64(<2 x i64> %a0) nounwind {
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; SSE-LABEL: test_mm_cvtsi128_si64:
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; SSE: # %bb.0:
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; SSE-NEXT: movq %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_cvtsi128_si64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovq %xmm0, %rax
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; AVX-NEXT: retq
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%res = extractelement <2 x i64> %a0, i32 0
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ret i64 %res
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}
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define <2 x double> @test_mm_cvtsi64_sd(<2 x double> %a0, i64 %a1) nounwind {
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; SSE-LABEL: test_mm_cvtsi64_sd:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtsi2sd %rdi, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_cvtsi64_sd:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtsi2sd %rdi, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1)
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
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define <2 x i64> @test_mm_cvtsi64_si128(i64 %a0) nounwind {
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; SSE-LABEL: test_mm_cvtsi64_si128:
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; SSE: # %bb.0:
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; SSE-NEXT: movq %rdi, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_cvtsi64_si128:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovq %rdi, %xmm0
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; AVX-NEXT: retq
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%res0 = insertelement <2 x i64> undef, i64 %a0, i32 0
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%res1 = insertelement <2 x i64> %res0, i64 0, i32 1
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ret <2 x i64> %res1
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}
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define i64 @test_mm_cvttsd_si64(<2 x double> %a0) nounwind {
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; SSE-LABEL: test_mm_cvttsd_si64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttsd2si %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_cvttsd_si64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttsd2si %xmm0, %rax
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; AVX-NEXT: retq
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%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
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define <2 x i64> @test_mm_loadu_si64(i64* %a0) nounwind {
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; SSE-LABEL: test_mm_loadu_si64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_mm_loadu_si64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%ld = load i64, i64* %a0, align 1
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%res0 = insertelement <2 x i64> undef, i64 %ld, i32 0
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%res1 = insertelement <2 x i64> %res0, i64 0, i32 1
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ret <2 x i64> %res1
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}
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define void @test_mm_stream_si64(i64 *%a0, i64 %a1) {
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; CHECK-LABEL: test_mm_stream_si64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movntiq %rsi, (%rdi)
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; CHECK-NEXT: retq
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store i64 %a1, i64* %a0, align 1, !nontemporal !0
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ret void
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}
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!0 = !{i64 1}
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