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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
29 lines
1.3 KiB
LLVM
29 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
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declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
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define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
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; CHECK-LABEL: crc32_64_8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
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; CHECK-NEXT: crc32b %sil, %eax ## encoding: [0xf2,0x40,0x0f,0x38,0xf0,0xc6]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
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ret i64 %tmp
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}
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define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: crc32_64_64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rdi, %rax ## encoding: [0x48,0x89,0xf8]
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; CHECK-NEXT: crc32q %rsi, %rax ## encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc6]
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; CHECK-NEXT: retq ## encoding: [0xc3]
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%tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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