mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
886fba1618
For example:
long long test(long long a, long long b) {
if (a << b > 0)
return b;
if (a << b < 0)
return a;
return a*b;
}
Produces:
sld. 5, 3, 4
ble 0, .LBB0_2
mr 3, 4
blr
.LBB0_2: # %if.end
cmpldi 5, 0
li 5, 1
isel 4, 4, 5, 2
mulld 3, 4, 3
blr
But the compare (cmpldi 5, 0) is redundant and can be removed (CR0 already
contains the result of that comparison).
The root cause of this is that LLVM converts signed comparisons into equality
comparison based on dominance. Equality comparisons are unsigned by default, so
we get either a record-form or cmp (without the l for logical) feeding a cmpl.
That is the situation we want to avoid here.
Differential Revision: https://reviews.llvm.org/D60506
616 lines
18 KiB
LLVM
616 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st -verify-machineinstrs < %s | FileCheck %s
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; Test cases are generated from:
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; long long NAME(PARAM a, PARAM b) {
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; if (LHS > RHS)
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; return b;
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; if (LHS < RHS)
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; return a;\
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; return a * b;
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; }
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; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
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; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
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target datalayout = "e-m:e-i64:64-n32:64"
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define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_op_b__2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rdx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shlq %cl, %rdx
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; CHECK-NEXT: cmpq $-2, %rdx
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; CHECK-NEXT: jg .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB0_2: # %return
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, %b
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%cmp = icmp sgt i64 %shl, -2
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i64 %shl, -2
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%mul = select i1 %cmp2, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_op_b__1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rdx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shlq %cl, %rdx
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; CHECK-NEXT: testq %rdx, %rdx
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; CHECK-NEXT: js .LBB1_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_1: # %if.end
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; CHECK-NEXT: cmpq $-1, %rdx
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, %b
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%cmp = icmp sgt i64 %shl, -1
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i64 %shl, -1
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%mul = select i1 %cmp2, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_op_b_0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rdx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shlq %cl, %rdx
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; CHECK-NEXT: testq %rdx, %rdx
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; CHECK-NEXT: jle .LBB2_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB2_1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovsq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, %b
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%cmp = icmp sgt i64 %shl, 0
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i64 %shl, 0
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%mul = select i1 %cmp2, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_op_b_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rdx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shlq %cl, %rdx
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; CHECK-NEXT: cmpq $1, %rdx
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; CHECK-NEXT: jg .LBB3_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: testq %rdx, %rdx
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovleq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB3_2: # %return
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, %b
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%cmp = icmp sgt i64 %shl, 1
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i64 %shl, 1
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%mul = select i1 %cmp2, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_op_b_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %rdi, %rdx
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shlq %cl, %rdx
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; CHECK-NEXT: cmpq $2, %rdx
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; CHECK-NEXT: jg .LBB4_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB4_2: # %return
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, %b
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%cmp = icmp sgt i64 %shl, 2
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i64 %shl, 2
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%mul = select i1 %cmp2, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a__2(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a__2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: cmpq $-2, %rdi
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; CHECK-NEXT: jg .LBB5_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB5_2: # %return
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp sgt i64 %a, -2
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp eq i64 %a, -2
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%mul = select i1 %cmp1, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a__1(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a__1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: js .LBB6_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB6_1: # %if.end
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; CHECK-NEXT: cmpq $-1, %rdi
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp sgt i64 %a, -1
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp eq i64 %a, -1
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%mul = select i1 %cmp1, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_0(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: jle .LBB7_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB7_1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovsq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp sgt i64 %a, 0
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp eq i64 %a, 0
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%mul = select i1 %cmp1, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_1(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: cmpq $1, %rdi
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; CHECK-NEXT: jg .LBB8_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovleq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB8_2: # %return
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp sgt i64 %a, 1
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp eq i64 %a, 1
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%mul = select i1 %cmp1, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @ll_a_2(i64 %a, i64 %b) {
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; CHECK-LABEL: ll_a_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: cmpq $2, %rdi
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; CHECK-NEXT: jg .LBB9_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: cmovlq %rcx, %rax
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; CHECK-NEXT: imulq %rdi, %rax
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; CHECK-NEXT: .LBB9_2: # %return
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp sgt i64 %a, 2
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = icmp eq i64 %a, 2
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%mul = select i1 %cmp1, i64 %b, i64 1
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%spec.select = mul nsw i64 %mul, %a
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ret i64 %spec.select
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return: ; preds = %entry
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ret i64 %b
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}
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define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: i_a_op_b__2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: cmpl $-2, %eax
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; CHECK-NEXT: jg .LBB10_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovll %eax, %ecx
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; CHECK-NEXT: imull %edi, %ecx
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; CHECK-NEXT: .LBB10_2: # %return
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; CHECK-NEXT: movslq %ecx, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i32 %a, %b
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%cmp = icmp sgt i32 %shl, -2
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i32 %shl, -2
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%mul = select i1 %cmp2, i32 %b, i32 1
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%spec.select = mul nsw i32 %mul, %a
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
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%retval.0 = sext i32 %retval.0.in to i64
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ret i64 %retval.0
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}
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define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: i_a_op_b__1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: js .LBB11_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: movslq %ecx, %rax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB11_1: # %if.end
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; CHECK-NEXT: cmpl $-1, %eax
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovll %eax, %ecx
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; CHECK-NEXT: imull %edi, %ecx
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; CHECK-NEXT: movslq %ecx, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i32 %a, %b
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%cmp = icmp sgt i32 %shl, -1
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i32 %shl, -1
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%mul = select i1 %cmp2, i32 %b, i32 1
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%spec.select = mul nsw i32 %mul, %a
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
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%retval.0 = sext i32 %retval.0.in to i64
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ret i64 %retval.0
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}
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define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: i_a_op_b_0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: jle .LBB12_1
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; CHECK-NEXT: # %bb.2: # %return
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; CHECK-NEXT: movslq %ecx, %rax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB12_1: # %if.end
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmovsl %eax, %ecx
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; CHECK-NEXT: imull %edi, %ecx
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; CHECK-NEXT: movslq %ecx, %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i32 %a, %b
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%cmp = icmp sgt i32 %shl, 0
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp eq i32 %shl, 0
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%mul = select i1 %cmp2, i32 %b, i32 1
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%spec.select = mul nsw i32 %mul, %a
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
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%retval.0 = sext i32 %retval.0.in to i64
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ret i64 %retval.0
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}
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define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: i_a_op_b_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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|
; CHECK-NEXT: cmpl $1, %eax
|
|
; CHECK-NEXT: jg .LBB13_2
|
|
; CHECK-NEXT: # %bb.1: # %if.end
|
|
; CHECK-NEXT: testl %eax, %eax
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovlel %eax, %ecx
|
|
; CHECK-NEXT: imull %edi, %ecx
|
|
; CHECK-NEXT: .LBB13_2: # %return
|
|
; CHECK-NEXT: movslq %ecx, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%shl = shl i32 %a, %b
|
|
%cmp = icmp sgt i32 %shl, 1
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp2 = icmp eq i32 %shl, 1
|
|
%mul = select i1 %cmp2, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a_op_b_2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: movl %esi, %ecx
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: shll %cl, %eax
|
|
; CHECK-NEXT: cmpl $2, %eax
|
|
; CHECK-NEXT: jg .LBB14_2
|
|
; CHECK-NEXT: # %bb.1: # %if.end
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovll %eax, %ecx
|
|
; CHECK-NEXT: imull %edi, %ecx
|
|
; CHECK-NEXT: .LBB14_2: # %return
|
|
; CHECK-NEXT: movslq %ecx, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%shl = shl i32 %a, %b
|
|
%cmp = icmp sgt i32 %shl, 2
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp2 = icmp eq i32 %shl, 2
|
|
%mul = select i1 %cmp2, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a__2(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a__2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: cmpl $-2, %edi
|
|
; CHECK-NEXT: jg .LBB15_2
|
|
; CHECK-NEXT: # %bb.1: # %if.end
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovll %eax, %esi
|
|
; CHECK-NEXT: imull %edi, %esi
|
|
; CHECK-NEXT: .LBB15_2: # %return
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%cmp = icmp sgt i32 %a, -2
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp1 = icmp eq i32 %a, -2
|
|
%mul = select i1 %cmp1, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a__1(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a__1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: testl %edi, %edi
|
|
; CHECK-NEXT: js .LBB16_1
|
|
; CHECK-NEXT: # %bb.2: # %return
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
; CHECK-NEXT: .LBB16_1: # %if.end
|
|
; CHECK-NEXT: cmpl $-1, %edi
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovll %eax, %esi
|
|
; CHECK-NEXT: imull %edi, %esi
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%cmp = icmp sgt i32 %a, -1
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp1 = icmp eq i32 %a, -1
|
|
%mul = select i1 %cmp1, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a_0(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a_0:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: testl %edi, %edi
|
|
; CHECK-NEXT: jle .LBB17_1
|
|
; CHECK-NEXT: # %bb.2: # %return
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
; CHECK-NEXT: .LBB17_1: # %if.end
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovsl %eax, %esi
|
|
; CHECK-NEXT: imull %edi, %esi
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%cmp = icmp sgt i32 %a, 0
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp1 = icmp eq i32 %a, 0
|
|
%mul = select i1 %cmp1, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a_1(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a_1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: cmpl $1, %edi
|
|
; CHECK-NEXT: jg .LBB18_2
|
|
; CHECK-NEXT: # %bb.1: # %if.end
|
|
; CHECK-NEXT: testl %edi, %edi
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovlel %eax, %esi
|
|
; CHECK-NEXT: imull %edi, %esi
|
|
; CHECK-NEXT: .LBB18_2: # %return
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%cmp = icmp sgt i32 %a, 1
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp1 = icmp eq i32 %a, 1
|
|
%mul = select i1 %cmp1, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|
|
|
|
define i64 @i_a_2(i32 signext %a, i32 signext %b) {
|
|
; CHECK-LABEL: i_a_2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: cmpl $2, %edi
|
|
; CHECK-NEXT: jg .LBB19_2
|
|
; CHECK-NEXT: # %bb.1: # %if.end
|
|
; CHECK-NEXT: movl $1, %eax
|
|
; CHECK-NEXT: cmovll %eax, %esi
|
|
; CHECK-NEXT: imull %edi, %esi
|
|
; CHECK-NEXT: .LBB19_2: # %return
|
|
; CHECK-NEXT: movslq %esi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%cmp = icmp sgt i32 %a, 2
|
|
br i1 %cmp, label %return, label %if.end
|
|
|
|
if.end: ; preds = %entry
|
|
%cmp1 = icmp eq i32 %a, 2
|
|
%mul = select i1 %cmp1, i32 %b, i32 1
|
|
%spec.select = mul nsw i32 %mul, %a
|
|
br label %return
|
|
|
|
return: ; preds = %if.end, %entry
|
|
%retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
|
|
%retval.0 = sext i32 %retval.0.in to i64
|
|
ret i64 %retval.0
|
|
}
|