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0620939033
Summary: Move reserveRegisterTuples into AMDGPURegisterInfo and use it in R600RegisterInfo::getReservedRegs and R600InstrInfo::reserveIndirectRegisters to ensure that all super registers of reserved registers are also marked as reserved. Before this change, under certain circumstances, the registers %t1_x and %t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not be, leading to the register allocator sometimes assigning a register to %t1_xy, which is invalid since %t1_x is reserved. Reviewers: arsenm, tstellar, MatzeB, qcolombet Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D42448 llvm-svn: 323356
40 lines
1.1 KiB
C++
40 lines
1.1 KiB
C++
//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
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#define GET_REGINFO_HEADER
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#include "AMDGPUGenRegisterInfo.inc"
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namespace llvm {
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class AMDGPUSubtarget;
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class TargetInstrInfo;
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struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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AMDGPURegisterInfo();
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/// \returns the sub reg enum value for the given \p Channel
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/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
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unsigned getSubRegFromChannel(unsigned Channel) const;
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void reserveRegisterTuples(BitVector &, unsigned Reg) const;
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};
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} // End namespace llvm
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#endif
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