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032b2a6c3d
https://reviews.llvm.org/D70210 Previously: Due to sensitivity of the algorithm with gaps, and extra instructions, when diffing, often we see naming being off by a few. Makes the diff unreadable even for tests with 7 and 8 instructions respectively. Naming can change depending on candidates (and order of picking candidates). Suddenly if there's one extra instruction somewhere, the entire subtree would be named completely differently. No consistent naming of similar instructions which occur in different functions. If we try to do something like count the frequency distribution of various differences across suite, then the above sensitivity issues are going to result in poor results. Instead: Name instruction based on semantics of the instruction (hash of the opcode and operands). Essentially for a given instruction that occurs in any module/function it'll be named similarly (ie semantic). This has some nice properties Can easily look at many instructions and just check the hash and if they're named similarly, then it's the same instruction. Makes it very easy to spot the same instruction both multiple times, as well as across many functions (useful for frequency distribution). Independent of traversal/candidates/depth of graph. No need to keep track of last index/gaps/skip count etc. No off by few issues with diffs. I've tried the old vs new implementation in files ranging from 30 to 700 instructions. In both cases with the old algorithm, diffs are a sea of red, where as for the semantic version, in both cases, the diffs line up beautifully. Simplified implementation of the main loop (simple iteration) , no keep track of what's visited and not. Handle collision just by incrementing a counter. Roughly bb[N]_hash_[CollisionCount]. Additionally with the new implementation, we can probably avoid doing the hoisting of instructions to various places, as they'll likely be named the same resulting in differences only based on collision (ie regardless of whether the instruction is hoisted or not/close to use or not, it'll be named the same hash which should result in use of the instruction be identical with the only change being the collision count) which is very easy to spot visually.
95 lines
3.4 KiB
C++
95 lines
3.4 KiB
C++
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//===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The purpose of these utilities is to abstract out parts of the MIRCanon pass
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// that are responsible for renaming virtual registers with the purpose of
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// sharing code with a MIRVRegNamer pass that could be the analog of the
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// opt -instnamer pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
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#define LLVM_LIB_CODEGEN_MIRVREGNAMERUTILS_H
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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/// VRegRenamer - This class is used for renaming vregs in a machine basic
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/// block according to semantics of the instruction.
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class VRegRenamer {
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class NamedVReg {
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Register Reg;
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std::string Name;
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public:
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NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {}
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NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {}
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const std::string &getName() const { return Name; }
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Register getReg() const { return Reg; }
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};
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MachineRegisterInfo &MRI;
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unsigned CurrentBBNumber = 0;
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/// Given an Instruction, construct a hash of the operands
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/// of the instructions along with the opcode.
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/// When dealing with virtual registers, just hash the opcode of
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/// the instruction defining that vreg.
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/// Handle immediates, registers (physical and virtual) explicitly,
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/// and return a common value for the other cases.
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/// Instruction will be named in the following scheme
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/// bb<block_no>_hash_<collission_count>.
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std::string getInstructionOpcodeHash(MachineInstr &MI);
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/// For all the VRegs that are candidates for renaming,
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/// return a mapping from old vregs to new vregs with names.
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std::map<unsigned, unsigned>
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getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
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/// Perform replacing of registers based on the <old,new> vreg map.
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bool doVRegRenaming(const std::map<unsigned, unsigned> &VRegRenameMap);
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public:
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VRegRenamer() = delete;
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VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {}
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/// createVirtualRegister - Given an existing vreg, create a named vreg to
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/// take its place. The name is determined by calling
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/// getInstructionOpcodeHash.
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unsigned createVirtualRegister(unsigned VReg);
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/// Create a vreg with name and return it.
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unsigned createVirtualRegisterWithName(unsigned VReg,
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const std::string &Name);
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/// Linearly traverse the MachineBasicBlock and rename each instruction's
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/// vreg definition based on the semantics of the instruction.
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/// Names are as follows bb<BBNum>_hash_[0-9]+
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bool renameInstsInMBB(MachineBasicBlock *MBB);
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/// Same as the above, but sets a BBNum depending on BB traversal that
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/// will be used as prefix for the vreg names.
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bool renameVRegs(MachineBasicBlock *MBB, unsigned BBNum = 0);
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unsigned getCurrentBBNumber() const { return CurrentBBNumber; }
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};
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} // namespace llvm
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#endif
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